Hi,
I changed the .md and .c file:
I add these lines to the .md file:
-----------------------------------------------------------------
(define_insn "ble1"
[(set (pc)
(if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:SI 1 "register_operand" "=d,d"))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"ble1\\t%0,%1,%2"
[(set_attr "type" "branch")
(set_attr "mode" "SI")])
(define_expand "cbranchsi4"
[(set (pc)
(if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
(match_operand:SI 1 "register_operand" "=d,d"))
(label_ref (match_operand 2 "" ""))
(pc)))]
""
"
{
gen_conditional_le (operands[0],operands[1],operands[2]);
DONE;
}")
-----------------------------------------------------------------
and add these lines to the .c file:
***************************************************
gen_conditional_le(rtx comp1, rtx comp2, rtx final_label)
{
printf("my operation called");
emit_insn(gen_ble1(comp1, comp2, final_label));
return TRUE;
}
***************************************************
but it didn't work...
I want the following C code is compiled to just one instruction:
if(a<=b)
c = 10;
asembly:
ble1 $1,$2,0x...
(a ===> $1 and b===> $2)
I appreciate it if you would guide me through this issue.
best regards
Ian Lance Taylor-3 wrote:
>
> yazdanbakhsh <[email protected]> writes:
>
>> I have read all the documents, and changed some lines but nothing
>> happened :(
>
> That is good, but to get help you really need to ask specific
> questions. Show us an insn pattern, tell us what you are trying to
> do, tell us what you did, tell us what happened.
>
> Ian
>
>> Ian Lance Taylor-3 wrote:
>>>
>>> yazdanbakhsh <[email protected]> writes:
>>>
>>>> I want to change instruction blez to ble. ble compare two registers and
>>>> jump
>>>> to the target address if the condition is true.
>>>
>>> Read the internals manual to understand how operand predicates and
>>> constraints work. See the hundreds of existing examples. Ask if you
>>> have specific questions.
>>>
>>> Ian
>>>
>>>> Ian Lance Taylor-3 wrote:
>>>>>
>>>>> yazdanbakhsh <[email protected]> writes:
>>>>>
>>>>>> Please assume I'm working with the MIPS. There is a little difference
>>>>>> between the MIPS and what I'm actually working on it. How can I
>>>>>> remove
>>>>>> immediate logical shift right/left from the compiler?
>>>>>> I mean If I want the programmer writes an immediate shift, It is
>>>>>> compiled
>>>>>> to
>>>>>> the two instructions:
>>>>>>
>>>>>> sll %2,%2,5
>>>>>>
>>>>>> changed to:
>>>>>>
>>>>>> addi %3,%0,5
>>>>>> sllv %2,%2,%3
>>>>>
>>>>> Find the insn which generates sll. Change the operand constraints and
>>>>> predicates to reject an immediate operand.
>>>>>
>>>>> E.g., in mips.md this is:
>>>>>
>>>>> (define_insn "*<optab><mode>3"
>>>>> [(set (match_operand:GPR 0 "register_operand" "=d")
>>>>> (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>>>> (match_operand:SI 2 "arith_operand" "dI")))]
>>>>> "!TARGET_MIPS16"
>>>>> {
>>>>> if (CONST_INT_P (operands[2]))
>>>>> operands[2] = GEN_INT (INTVAL (operands[2])
>>>>> & (GET_MODE_BITSIZE (<MODE>mode) - 1));
>>>>>
>>>>> return "<d><insn>\t%0,%1,%2";
>>>>> }
>>>>> [(set_attr "type" "shift")
>>>>> (set_attr "mode" "<MODE>")])
>>>>>
>>>>>
>>>>> For operand 2, change the predicate to register_operand and remove the
>>>>> 'I' constraint.
>>>>>
>>>>> Ian
>>>>>
>>>>>
>>>>
>>>> --
>>>> View this message in context:
>>>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28447744.html
>>>> Sent from the gcc - Dev mailing list archive at Nabble.com.
>>>
>>>
>>
>> --
>> View this message in context:
>> http://old.nabble.com/Question-about-Machine-Description-tp1026428p28449607.html
>> Sent from the gcc - Dev mailing list archive at Nabble.com.
>
>
--
View this message in context:
http://old.nabble.com/Question-about-Machine-Description-tp1026428p28476454.html
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