[EMAIL PROTECTED] wrote on 26/02/2007 10:40:59:
>I am targeting GCC 4.1.1 to a custom RISC processor; which has some vector
>instructions (32 bit vectors). It can perform two 16 bit/ or four 8 bit
>additions, subtractions, multiplications & shift operations
simultaneously.
>I would like to use t
You'll want to have a look at something like the SSE SIMD optimisation within
the back end for the x86.
I'd also download the GCC internals document for 4.3.x as it has some
information on CPU SIMD optimisations.
I've been reviewing this area heavily as I'm combining GCC and GPGPU (the same
id
On Fri, Feb 23, 2007 at 04:13:39PM -0800, sdutta wrote:
> I am targeting GCC 4.1.1 to a custom RISC processor; which has some vector
> instructions (32 bit vectors). It can perform two 16 bit/ or four 8 bit
> additions, subtractions, multiplications & shift operations simultaneously.
>
> I would l
