Den 2019-11-12 kl. 19:54, skrev Jeff Law:
On 11/12/19 11:29 AM, m wrote:
Hello gcc developers!
I am working on a new back end for my MRISC32 ISA [1], and I'm still very
new to gcc internals. I suspect that I will have more questions further
down the road, but let's start with this topic...
The
On 11/12/19 11:29 AM, m wrote:
> Hello gcc developers!
>
> I am working on a new back end for my MRISC32 ISA [1], and I'm still very
> new to gcc internals. I suspect that I will have more questions further
> down the road, but let's start with this topic...
>
> The MRISC32 ISA has instructions f
Hello gcc developers!
I am working on a new back end for my MRISC32 ISA [1], and I'm still very
new to gcc internals. I suspect that I will have more questions further
down the road, but let's start with this topic...
The MRISC32 ISA has instructions for setting a register based on the
outcome o
On 01/24/2017 03:24 PM, Dimitar Dimitrov wrote:
Currently I'm attempting to describe the 8-bit PRU subregisters as the "real"
target register set, and then work on defining 16-bit and 32-bit ALU operations. But I'm
not sure if that would be efficient for a 32-bit PRU target, or feasible at al
Hello,
I'm a newbie working on a GCC port [1] for PRU [2]. In order to achieve ABI
compatibility with the proprietary TI toolchain, I need my Machine Description
to support HW register subfields as indipendent first-class registers. I could
not find a relevant example in the GCC source.
On Thu, 27 Nov 2014, Mathias Roslund wrote:
> But isn't the result of an 8bit signed divide the same as the result of
> a 32bit signed divide when both operands are in the 8bit range? That is,
> shouldn't the optimizers be able to do the same for signed divide as
> well as shift operations?
At
> From: Joern Rennecke [mailto:joern.renne...@embecosm.com]
> Sent: Wednesday, November 26, 2014 6:13 PM
> To: Mathias Roslund
> Cc: GCC
> Subject: Re: Machine description and code generation
>
> On 26 November 2014 at 16:48, Mathias Roslund
> wrote:
> > Since the
On 26 November 2014 at 16:48, Mathias Roslund wrote:
> Since then I've added more instructions and gotten to the point where most
> stuff seems to be working. My current issue is that signed divide and all
> shift operations insists on sign/zero extending the operands, resulting in
> 32bit operati
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On Behalf Of
> Jeff Law
> Sent: Wednesday, October 29, 2014 9:36 PM
> To: Mathias Roslund; gcc@gcc.gnu.org
> Subject: Re: Machine description and code generation
>
> On 10/29/14 07:40, Mathias Roslund wrote:
&
On 10/29/14 07:40, Mathias Roslund wrote:
Hello,
I'm considering attempting a 65816 target but decided it would be a good
idea to start with something simple in order to learn how GCC generate
code. So I created a minimal machine description with just two
instructions (plus the mandator
Hello,
I'm considering attempting a 65816 target but decided it would be a good
idea to start with something simple in order to learn how GCC generate
code. So I created a minimal machine description with just two
instructions (plus the mandatory nop/jump/etc):
(define_mode_iterator INT [
Thanks Richard,
The penny dropped when I read your comment about the % operator. item
(2) send me back to the gcc internals document (again !) and I had the
problem sorted in about half an hour.
Thanks again,
Paul.
On 06/01/12 08:23, Richard Henderson wrote:
On 01/05/2012 10:33 PM, Paul S w
On 01/05/2012 10:33 PM, Paul S wrote:
> (define_insn "addqi3i"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (plus:HI (match_operand:HI 1 "register_operand" "%0")
> (sign_extend:HI (match_operand:QI 2 "memory_operand" "m"]
Two things are wrong with this pattern:
(1) % is incorrect b
I've been trying off and on for a couple of days to create a machine
description that handles the following target and produces the output I
am hoping for.
The CPU has a 16 bit word size - and only has word size registers. As a
consequence it sign or zero extends when loading byte ope
yazdanbakhsh writes:
> I'm working with GCC 2.7.
I think I see your problem.
> I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
>
> int
> new_arith_operand (op, mode)
> rtx op;
> enum machine_mode mode;
> {
> if (GE
Actually, I'm working with simplescalar and it only supports gcc 2.9.
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On 15 June 2010 14:01, yazdanbakhsh wrote:
>
> I'm working with GCC 2.7. I think, It doesn't support define_predict.
> I define a c function in the mips.c file and add the following lines:
[...]
> I appreciate any help.
I think the best advice I can give you is: Use a recent GCC version.
GCC 2.7
le.com/Question-about-Machine-Description-tp1026428p28890399.html
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Hello,
> I want to limit the size of immediate field of some operation.
I think you can look at SIGNED_INT_FITS_N_BITS definition at
config/crx/crx.c
for such example.
You can write a predicate like the following; and use it when describing
the immediate
operand in the md file.
(define_predicate
Hi,
I want to limit the size of immediate field of some operation. For example
somehow modify the machine description that the compiler supports only 0-255
for immediate operand.
I also want to change the compiler to the 2-address operand.
do you have any ideas?
I just need some hint
Best
yazdanbakhsh writes:
> I did what you said, and the same error happened :(
I'm sorry you're having trouble, but if you want us to be able to help
you you need to show us precisely what you did, precisely what
happened, and what you expected to happen.
Ian
I did what you said, and the same error happened :(
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yazdanbakhsh writes:
> I want to exclude all immediate or instruction. I did this by the following
> define_insn
>
> /--
> (define_insn "iorsi3"
> [(set (match_operand:SI 0 "register_operand" "=d,d")
> (ior:SI (m
Internal compiler error: program cc1 got fatal signal 6
make: *** [libgcc2.a] Error 1
//----------
I appreciate any help.
Bestr
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yazdanbakhsh writes:
> I want to exclude XORI from the instruction set of a cpu. I deleted all the
> XORI in md file. But when I compiled my program some XORI operation still
> exist. how this would be possible?
It could be printed directly from a .c file in your config/CPU
directory.
Ian
Hi,
I want to exclude XORI from the instruction set of a cpu. I deleted all the
XORI in md file. But when I compiled my program some XORI operation still
exist. how this would be possible?
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instruction that should be
moved but not?
Cheers,
Bingfeng
-Original Message-
From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
Sent: 14 May 2010 12:26
To: Bingfeng Mei
Cc: gcc@gcc.gnu.org
Subject: Re: Machine description question
Hi Bengfeng,
Changing my instruction patterns
iharan Sandanagobalane [mailto:harihar...@picochip.com]
> Sent: 14 May 2010 12:26
> To: Bingfeng Mei
> Cc: gcc@gcc.gnu.org
> Subject: Re: Machine description question
>
> Hi Bengfeng,
> Changing my instruction patterns similar to the ones that you
> sent does
> get over t
ll porivate and not in mainline.
Cheers,
Bingfeng
-Original Message-
From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
Sent: 13 May 2010 10:17
To: Bingfeng Mei
Cc: gcc@gcc.gnu.org
Subject: Re: Machine description question
The patterns for PUT/GET were
; Scalar Pu
BXM))
(unspec:BXBC [(reg:BXBC R_BX)] UNSPEC_BX)] < Important to avoid some
optimization.
Our port is still porivate and not in mainline.
Cheers,
Bingfeng
> -Original Message-
> From: Hariharan Sandanagobalane [mailto:harihar...@picochip.com]
> Sent: 13 May 201
with same parameters would result in same value being produced. This
obviously is not the case for these communication instructions.
Do you have your code to do this using unspec in gcc mainline? Can you
point me to that, please?
Thanks
Hari
Bingfeng Mei wrote:
How do you define your imaginary register
g
> Subject: Re: Machine description question
>
> Thanks for your help BingFeng.
>
> I gave this a go and ended up with worse code (and worse
> memory usage)
> than before. I started with this experiment because of the compilers
> "All virtual regis
vent some wrong optimizations.
Cheers,
Bingfeng
-Original Message-
From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On
Behalf Of Hariharan
Sent: 12 May 2010 11:18
To: gcc@gcc.gnu.org
Subject: Machine description question
Hello all,
Picochip has communication instructions
independent expression in your pattern to prevent some wrong optimizations.
Cheers,
Bingfeng
> -Original Message-
> From: gcc-ow...@gcc.gnu.org [mailto:gcc-ow...@gcc.gnu.org] On
> Behalf Of Hariharan
> Sent: 12 May 2010 11:18
> To: gcc@gcc.gnu.org
> Subject: Machine de
Hello all,
Picochip has communication instructions that allow one array element to
pass data to another. There are 3 such instructions PUT/GET/TSTPORT.
Currently, all three of these use UNSPEC_VOLATILE side-effect
expressions to make sure they don't get reordered. But, i wonder if it
is an ove
yazdanbakhsh writes:
> (define_insn "*bltdf"
> [(set (pc)
> (if_then_else (lt:SI (match_operand:DF 1 "" "")
>(match_operand:DF 2 "" ""))
> (match_operand 3 "pc_or_label_operand" "")
> (match_operand 4 "pc_or_label_operand" "")))]
> ""
>
> "*
> {
ng line to the mips-opc.c:
{"blt", "s,t,p",0x000d, 0x0000, 0 },
but during cmpilation, I encounter the following error:
...
_ashrdi3
_ffsdi2
_udiv_w_sdiv
_udivmoddi4
_cmpdi2
_ucmpdi2
_floatdidf
_floatdisf
_fixunsdfsi
_fixunssfsi
_fixunsdfdi
/tmp/ccrWquNC.s: Assembler messages:
/tmp/ccrWquNC.s:169: Error: illegal operands `blt'
/tmp/ccrWquNC.s:231: Error: illegal operands `blt'
make: *** [libgcc2.a] Error 1
I appreciate any help...
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yazdanbakhsh writes:
> (define_expand "cbranchsi4"
> [(set (pc)
> (if_then_else: SI (le:SI (match_operand:SI 0 "register_operand" "=d,d")
> (match_operand:SI 1 "register_operand" "=d,d"))
> (label_ref (match_operand 2 "" ""))
> (pc)))]
> ""
> "
s to reject an immediate operand.
>>>>>
>>>>> E.g., in mips.md this is:
>>>>>
>>>>> (define_insn "*3"
>>>>> [(set (match_operand:GPR 0 "register_operand" "=d")
>>>>> (any_shift:GP
e insn which generates sll. Change the operand constraints and
>>>> predicates to reject an immediate operand.
>>>>
>>>> E.g., in mips.md this is:
>>>>
>>>> (define_insn "*3"
>>>> [(set (match_operand:GPR 0 "register_operand" &qu
t;>>> (define_insn "*3"
>>>> [(set (match_operand:GPR 0 "register_operand" "=d")
>>>>(any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
>>>> (match_operand:SI 2 "arith_operand" &q
>>> if (CONST_INT_P (operands[2]))
>>> operands[2] = GEN_INT (INTVAL (operands[2])
>>>& (GET_MODE_BITSIZE (mode) - 1));
>>>
>>> return "\t%0,%1,%2";
>>> }
>>> [(set_attr "type" "shift")
>>>(set_attr "mode" "")])
>>>
>>>
>>> For operand 2, change the predicate to register_operand and remove the
>>> 'I' constraint.
>>>
>>> Ian
>>>
>>>
>>
>> --
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>> Sent from the gcc - Dev mailing list archive at Nabble.com.
>
>
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if (CONST_INT_P (operands[2]))
>> operands[2] = GEN_INT (INTVAL (operands[2])
>> & (GET_MODE_BITSIZE (mode) - 1));
>>
>> return "\t%0,%1,%2";
>> }
>> [(set_attr "type" "shift")
>>(set_attr "mode" "")])
>>
>>
>> For operand 2, change the predicate to register_operand and remove the
>> 'I' constraint.
>>
>> Ian
>>
>>
>
> --
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> Sent from the gcc - Dev mailing list archive at Nabble.com.
> {
> if (CONST_INT_P (operands[2]))
> operands[2] = GEN_INT (INTVAL (operands[2])
> & (GET_MODE_BITSIZE (mode) - 1));
>
> return "\t%0,%1,%2";
> }
> [(set_attr "type" "shift")
>(set_attr "mode" &
yazdanbakhsh writes:
> This is the newer version. It works correctly. I just want know is there any
> other way.
Did you read what I wrote earlier?
http://gcc.gnu.org/ml/gcc/2010-05/msg00048.html
Ian
slav" (immediate arithmetic shift) from the
> instruction set. I explore ss.md file but I didn't see any define_ins for
> the mentioned instructions, but they are used in other instruction
> definitions.
> It is also exist for addi/addui. Where I can find the definitions of the
t;>>> instructions? I want to force gcc to just use register shift and
>>>> register
>>>> add.
>>>
>>> There is no ss.md file in the standard gcc distribution. If
>>> SimpleScalar has a gcc port, I don't know anything about it. So it's
>>> hard to answer to your question precisely.
>>>
>>> Instructions can come from either a .md file or a .c file in the
>>> config/CPU directory used for your CPU. If those instructions are
>>> appearing in the generated assembler, then they must be in there
>>> somewhere.
>>>
>>> Ian
>>>
>>>
>>
>>
>
>
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gt;> There is no ss.md file in the standard gcc distribution. If
>> SimpleScalar has a gcc port, I don't know anything about it. So it's
>> hard to answer to your question precisely.
>>
>> Instructions can come from either a .md file or a .c file in the
>> c
yazdanbakhsh writes:
> Please assume I'm working with the MIPS. There is a little difference
> between the MIPS and what I'm actually working on it. How can I remove
> immediate logical shift right/left from the compiler?
> I mean If I want the programmer writes an immediate shift, It is compiled
; hard to answer to your question precisely.
>
> Instructions can come from either a .md file or a .c file in the
> config/CPU directory used for your CPU. If those instructions are
> appearing in the generated assembler, then they must be in there
> somewhere.
>
> Ian
>
yazdanbakhsh writes:
> I'm working on my a gcc compiler for my own written processor with the help
> of SimpleScalar.
> I want to remove "srav/slav" (immediate arithmetic shift) from the
> instruction set. I explore ss.md file but I didn't see any define_ins for
> the mentioned instructions, but
but they are used in other instruction
definitions.
It is also exist for addi/addui. Where I can find the definitions of these
instructions? I want to force gcc to just use register shift and register
add.
Best Regards,
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On Fri, Jun 05, 2009 at 05:11:06PM -0500, Graham Reitz wrote:
>
> Is there a machine description template in the gcc file source tree?
>
> If there is also template for the 'C header file of macro definitions'
> that would be good to know too.
>
> I did a file
s/incrementalMD.pdf
which describes creation of a new, clean machine description from scratch
M
Graham Reitz wrote:
Is there a machine description template in the gcc file source tree?
If there is also template for the 'C header file of macro definitions'
that would be good to know too.
I did a file search for '.md' and there are tons of examples.
Although, I
The trick past there is to compare the significant features of your
machine with existing machines. For example, GCC prefers a 68000
style machine with a set of condition codes, however many machines
only have one condition flag that changes meaning based on what you
are doing.
-- Michael
2009/
the significant features of your
machine with existing machines. For example, GCC prefers a 68000
style machine with a set of condition codes, however many machines
only have one condition flag that changes meaning based on what you
are doing.
-- Michael
2009/6/6 Graham Reitz :
>
> Is there
On Fri, Jun 5, 2009 at 11:11 PM, Graham Reitz wrote:
>
> Is there a machine description template in the gcc file source tree?
There is no template as such but you could look at existing ports for
the basic templates. Google should give you results for previous
questions on this list regardi
Is there a machine description template in the gcc file source tree?
If there is also template for the 'C header file of macro definitions'
that would be good to know too.
I did a file search for '.md' and there are tons of examples.
Although, I was curious if
Jean Christophe Beyler writes:
> For the moment, no change, the expansion code is actually not used in
> this case because GCC only presents me with the load from a global
> during or after reload. Therefore, it's already done and he doesn't
> seem to want to change his ways. I haven't played wit
x_cost
but that's my next step.
Any comments, ideas?
Jc
On Wed, Apr 22, 2009 at 4:08 PM, Ian Lance Taylor wrote:
> Jean Christophe Beyler writes:
>
>> I've been working on the Machine description of my target and was
>> wondering if you could help me out here.
>>
>
Jean Christophe Beyler writes:
> I've been working on the Machine description of my target and was
> wondering if you could help me out here.
>
> I've been trying to force GCC out of it's habit of generating this code :
> (insn 28 8 10 2 glob.c:13 (set (re
Dear all,
I've been working on the Machine description of my target and was
wondering if you could help me out here.
I've been trying to force GCC out of it's habit of generating this code :
(insn 28 8 10 2 glob.c:13 (set (reg:DI 9 r9)
(mem/s:DI (symbol_ref:DI ("data&
Hi, thanks for your help!
stage 1 gcc compiled with the modified "callz" instruction.
The "callz" instruction showed up in my assembly dump now!!
Thanks so much,
David.
2009/3/13 Ian Lance Taylor :
>
> Part of stage 1 involves building the runtime support library. This is
> needed in order to b
dhua026 dhua026 writes:
> but most importantly, it used the "callz" instruction:
> /tmp/ccshjbUO.s: Assembler messages:
> /tmp/ccshjbUO.s:41: Error: no such instruction: `callz __fixunss...@plt'
> /tmp/ccshjbUO.s:53: Error: no such instruction: `callz __fixunss...@plt'
> make[1]: *** [_fixsfdi.o]
Hi all,
I am a newbie to GCC, but have long wanted to work with it. So I got
the chance to work on it with a research project, what I am trying to
do is add a custom backend to the GCC framework through machine
descriptions. I got the release sources (not from the SVN repository,
4.3.3), and foll
Ok, I understand now. Thank you very much for your explanations,
Jean Christophe Beyler
On Sat, Feb 7, 2009 at 5:13 PM, Michael Meissner
wrote:
> On Sat, Feb 07, 2009 at 03:54:51PM -0500, Jean Christophe Beyler wrote:
>> Dear all,
>>
>> I have a question about the way th
On Sat, Feb 07, 2009 at 03:54:51PM -0500, Jean Christophe Beyler wrote:
> Dear all,
>
> I have a question about the way the machine description works and how
> it affects the different passes of the compiler. I was reading the GNU
> Compiler Collection Internals and I found this p
Dear all,
I have a question about the way the machine description works and how
it affects the different passes of the compiler. I was reading the GNU
Compiler Collection Internals and I found this part (in section
14.8.1):
(define_insn ""
[(set (match_operand:SI 0 "
> When the offsets stored in the instructions are used, they refer to
> offsets from the address of the instruction (IA) plus 8 bytes. Are the
> pool_ranges also calculated from IA+8, from the address of the
> instruction itself or even from the address of the following
> instruction (IA+4)?
>
> In
and which need reimplementing, and to distill
the essence of them into one "proper" set, but each day I'm ending up
confused by too many things about MDs that I am not certain of, so
some help would be appreciated.
On with the first question...
ARM machine description and pool rang
just a that we are trying to set 1 byte of a
> memory location with the value in register #16 (r16) with an offset of
> 0which I have handled already in my machine description...so what
> can this be?
>
> Any help is highly appreciated.
>
> Thanking You,
>
> Yours Sin
r16) with an offset of
0which I have handled already in my machine description...so what
can this be?
Any help is highly appreciated.
Thanking You,
Yours Sincerely,
Balaji V. Iyer.
--
Balaji V. Iyer
PhD Student,
Center for Efficient, Scalable and Reliable Computing,
Department
dot gnu dot org, Richard dot Earnshaw at arm dot com
Date: Thu, 13 Mar 2003 09:45:08 +
Subject: Re: Supporting multiple instructions sets within a single machine description
Organization: ARM Ltd.
Reply-to: Richard dot Earnshaw at arm dot com
On Wed, 12 Mar 2003, Jon Beniston wrote:
>
Ian Lance Taylor writes:
> This kind of error generally means that the operand predicate accepts
> an operand which no constraint matches. If the predicate (e.g.,
> register_operand) accepts an operand, then there must be a constraint
> that matches it. Otherwise you will get an error in
> const
"Balaji V. Iyer" <[EMAIL PROTECTED]> writes:
> Thank you very much Ian and Shreyas for your quick response. So I guess,
> my question now would be, what would be an exmple that matches this
> constraint below?
>
> ((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
> (co
Thank you very much Ian and Shreyas for your quick response. So I guess,
my question now would be, what would be an exmple that matches this
constraint below?
((insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (r
"Balaji V. Iyer" <[EMAIL PROTECTED]> writes:
No need to send to both gcc@gcc.gnu.org and [EMAIL PROTECTED] I
removed gcc-help in this reply. Thanks.
>I am currently developing a GCC port for my own generic 32 bit
> processor. I have this following error when I tried to compile a
> benchmark
Hi all,
I am currently developing a GCC port for my own generic 32 bit
processor. I have this following error when I tried to compile a
benchmark.
(insn 1497 1924 1756 2 (set (mem:BI (plus:SI (reg/f:SI 2 r2)
(const_int -137 [0xff77])) [72 S1 A8])
(le:BI (reg:SI 12 r1
> Peter Steinmetz writes:
Peter> If I see the following on an instruction definition:
Peter> (set_attr "type" "*")
Peter> What does * represent in this context as the value to assign to "type"?
The default value specified when the attr "type" is defined.
David
Quick question on syntax in md files as I'm not finding the documentation
to explain it. If I see the following on an instruction definition:
(set_attr "type" "*")
What does * represent in this context as the value to assign to "type"?
Thanks.
Pete
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