On Wed, 2009-09-02 at 11:49 -0400, Vladimir Makarov wrote:
> So probably, it is worth to do update_equiv_reg as a separate pass.
Agreed.
> I'll submit a patch on next week (sorry, I am a bit busy this week).
Sounds good. Thanks for taking care of this!
Peter
Peter Bergner wrote:
On Tue, 2009-09-01 at 16:46 -0400, Vladimir Makarov wrote:
Peter Bergner wrote:
Were you going to whip that patch up or did you want me to?
I am going to do it by myself.
Great! I'd like to see how your patch affects POWER6 performance.
Do you have
On Tue, 2009-09-01 at 16:46 -0400, Vladimir Makarov wrote:
> Peter Bergner wrote:
> > Were you going to whip that patch up or did you want me to?
> >
> I am going to do it by myself.
Great! I'd like to see how your patch affects POWER6 performance.
Do you have access to a POWER6 box? If not, can
Peter Bergner wrote:
On Tue, 2009-09-01 at 10:38 -0400, Vladimir Makarov wrote:
We could do update_equiv_regs in a separate pass before the 1st insn
scheduling as it was before IRA.
IIRC, update_equiv_regs() was always called as part of local-alloc,
so it was always after sched1 even b
On Tue, 2009-09-01 at 10:38 -0400, Vladimir Makarov wrote:
> We could do update_equiv_regs in a separate pass before the 1st insn
> scheduling as it was before IRA.
IIRC, update_equiv_regs() was always called as part of local-alloc,
so it was always after sched1 even before IRA. That said, movin
On Wed, 2009-08-26 at 17:12 -0500, Peter Bergner wrote:
> On Wed, 2009-08-26 at 23:30 +0200, Richard Guenther wrote:
> > Hmm. I suppose if you conditionalize it on flag_schedule_insns it might be
> > an overall win. Care to SPEC test that change?
>
> I assume you mean like the change below? Yea
Peter Bergner wrote:
On Mon, 2009-08-24 at 23:56 +, Charles J. Tabony wrote:
I am seeing a performance regression on the port I maintain, and I would
appreciate some pointers.
When I compile the following code
void f(int *x, int *y){
*x = 7;
*y = 4;
}
with GCC 4.3.2, I get the des
On 08/27/09 04:04, Alex Turjan wrote:
With 4.4, IRA happens to reuse the same register for both pseudos, so
sched2 is hand tied and cannot schedule them back again for us.
I can imagine compiling other programs for which preserving the 4.3 allocation
will induce performance degradation du
oduces 2 registers.
--- On Wed, 8/26/09, Peter Bergner wrote:
> From: Peter Bergner
> Subject: Re: IRA undoing scheduling decisions
> To: "Charles J. Tabony"
> Cc: gcc@gcc.gnu.org
> Date: Wednesday, August 26, 2009, 11:47 PM
> On Mon, 2009-08-24 at 23:56 +,
&
On Wed, 2009-08-26 at 23:30 +0200, Richard Guenther wrote:
> On Wed, Aug 26, 2009 at 10:47 PM, Peter Bergner wrote:
> > Looking at update_equiv_regs(), if I disable the replacement for regs
> > that are local to one basic block (patch below) like it existed before
> > John Wehle's patch way back in
On Wed, Aug 26, 2009 at 10:47 PM, Peter Bergner wrote:
> On Mon, 2009-08-24 at 23:56 +, Charles J. Tabony wrote:
>> I am seeing a performance regression on the port I maintain, and I would
>> appreciate some pointers.
>>
>> When I compile the following code
>>
>> void f(int *x, int *y){
>> *
On Mon, 2009-08-24 at 23:56 +, Charles J. Tabony wrote:
> I am seeing a performance regression on the port I maintain, and I would
> appreciate some pointers.
>
> When I compile the following code
>
> void f(int *x, int *y){
> *x = 7;
> *y = 4;
> }
>
> with GCC 4.3.2, I get the desired
Charles J. Tabony writes:
> Filed as PR 41171.
Thanks.
> Is this actually a performance regression on MIPS? I suspect either
> sequence would be the same performance on most machines.
Yes it is: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=41171#c1
Adam
Adam Nemet wrote:
> "Charles J. Tabony" writes:
> > I see the same difference between GCC 4.3.2 and 4.4.0 when compiling
> > for PowerPC, MIPS, ARM, and FR-V.
>
> I can confirm this with mainline on MIPS/Octeon. Can you please file a
> bug.
Filed as PR 41171.
Is this actually a performa
gcc@gcc.gnu.org
> Subject: IRA undoing scheduling decisions
>
> Fellow GCC developers,
>
> I am seeing a performance regression on the port I maintain,
> and I would appreciate some pointers.
>
> When I compile the following code
>
> void f(int *x, int *y){
> *x
"Charles J. Tabony" writes:
> I see the same difference between GCC 4.3.2 and 4.4.0 when compiling
> for PowerPC, MIPS, ARM, and FR-V.
I can confirm this with mainline on MIPS/Octeon. Can you please file a
bug.
Adam
Fellow GCC developers,
I am seeing a performance regression on the port I maintain, and I would
appreciate some pointers.
When I compile the following code
void f(int *x, int *y){
*x = 7;
*y = 4;
}
with GCC 4.3.2, I get the desired sequence of instructions. I'll call it
sequence A:
r0 =
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