Fellow GCC developers,
I am seeing a performance regression on the port I maintain, and I would
appreciate some pointers.
When I compile the following code
void f(int *x, int *y){
*x = 7;
*y = 4;
}
with GCC 4.3.2, I get the desired sequence of instructions. I'll call it
sequence A:
r0 = 7
r1 = 4
[x] = r0
[y] = r1
When I compile the same code with GCC 4.4.0, I get a sequence that is lower
performance for my target machine. I'll call it sequence B:
r0 = 7
[x] = r0
r0 = 4
[y] = r0
I see the same difference between GCC 4.3.2 and 4.4.0 when compiling for
PowerPC, MIPS, ARM, and FR-V.
When I look at the RTL dumps, I see that the first scheduling pass always
produces sequence A, across all targets and GCC versions I tried. In GCC
4.3.2, sequence A persists throughout the remainder of compilation. In GCC
4.4.0, for every target, the .ira dump shows that the sequence of instructions
has reverted back to sequence B.
Are there any machine-dependent parameters that I can tune to prevent IRA from
transforming sequence A into sequence B? If not, where can I add a hook to
allow this decision to be tuned per machine?
Is there any more information you would like me to provide?
Thank you,
Charles J. Tabony
