On 22/05/2019 15:42, Szabolcs Nagy wrote:
> [AAELF64]: ELF for the Arm 64-bit Architecture (AArch64)
>https://developer.arm.com/docs/ihi0056/latest
> [VABI64]: Vector Function ABI Specification for AArch64
>
> https://developer.arm.com/tools-and-software/server-and-hpc/arm-
On 22/05/2019 16:34, Florian Weimer wrote:
> * Szabolcs Nagy:
>
>> On 22/05/2019 16:06, Florian Weimer wrote:
>>> * Szabolcs Nagy:
>>>
AAELF64: in the Symbol Table section add
st_other Values
The st_other member of a symbol table entry specifies the symbol's
* Szabolcs Nagy:
> On 22/05/2019 16:06, Florian Weimer wrote:
>> * Szabolcs Nagy:
>>
>>> AAELF64: in the Symbol Table section add
>>>
>>> st_other Values
>>> The st_other member of a symbol table entry specifies the symbol's
>>> visibility in the lowest 2 bits. The top 6 bits are
On 22/05/2019 16:06, Florian Weimer wrote:
> * Szabolcs Nagy:
>
>> AAELF64: in the Symbol Table section add
>>
>> st_other Values
>> The st_other member of a symbol table entry specifies the symbol's
>> visibility in the lowest 2 bits. The top 6 bits are unused in the
>> g
* Szabolcs Nagy:
> AAELF64: in the Symbol Table section add
>
> st_other Values
> The st_other member of a symbol table entry specifies the symbol's
> visibility in the lowest 2 bits. The top 6 bits are unused in the
> generic ELF ABI [SCO-ELF], and while there are no val
The lazy binding code of aarch64 currently only preserves q0-q7 of the
fp registers, but for an SVE call [AAPCS64+SVE] it should preserve p0-p3
and z0-z23, and for an AdvSIMD vector call [VABI64] it should preserve
q0-q23. (Vector calls are extensions of the base PCS [AAPCS64].)
A possible fix is
