On 10-Aug-16 08:41 PM, Vladimir N Makarov wrote:
As for memory constraint you should not to return true for a pseudo.
Reload/LRA can figure out how to match a spilled pseudo with memory
(but this constraint should be define_memory_constraint, i saw
mistakes when people used different forms of
On 10-Aug-16 08:41 PM, Vladimir N Makarov wrote:
On 08/09/2016 12:33 AM, shmeel gutl wrote:
On 03-Aug-16 12:10 AM, Vladimir Makarov wrote:
On 08/02/2016 04:41 PM, shmeel gutl wrote:
I am trying to enable lra for a propriety backend. I ran into one
problem that I can't solve. I
On 03-Aug-16 12:10 AM, Vladimir Makarov wrote:
On 08/02/2016 04:41 PM, shmeel gutl wrote:
I am trying to enable lra for a propriety backend. I ran into one
problem that I can't solve. In lra-constraints.c:split_reg
lra_create_new_reg can be called with a hard code rclass of NO_REGS.
It
I am trying to enable lra for a propriety backend. I ran into one
problem that I can't solve. In lra-constraints.c:split_reg
lra_create_new_reg can be called with a hard code rclass of NO_REGS. It
then queues a move instruction of the type
set TYPE:new_reg TYPE:old_reg
But the NO_REGS rclas
On 03-Jun-15 09:39 AM, shmeel gutl wrote:
find_modifiable_mems was introduced to gcc 4.8 in september 2012. Is
there any documentation as to how it is supposed to help the haifa
scheduler?
In my private port of gcc it make the following type of transformations
from
a= *(b+20
I am trying to enable lra for my vliw architecture and I am encountering
a problem of "max number of generated reload insns". The problem seems
elementary but I don't see the correction.
Consider
r1 =r2+r3
s1=r1+r4
call func(r3)
r5=s2+r1
where s registers are pseudo registers
On 01-Sep-15 01:54 PM, Eric S. Raymond wrote:
What kind of mechanical transformation or hand-editing would add value for you?
I am working from a clone of the current git repository. Is there an
automated procedure that will enable me to switch to the new repository
and still keep all of the co
On 31-Aug-15 02:19 PM, Richard Biener wrote:
On Mon, Aug 31, 2015 at 6:51 AM, shmeel gutl
wrote:
When dealing with an array with known values, pre will evaluate the first
iteration of a loop over the elements. The code generator with then jump
into the loop. This is at best increasing the
When dealing with an array with known values, pre will evaluate the
first iteration of a loop over the elements. The code generator with
then jump into the loop. This is at best increasing the size of the
code. It also creates inferior code when the hardware supports zero
overhead loops. The at
are there any guidelines as to what needs to be done in the backend to
enable lra for 5.2? when I turn it on I get two types of errors. 1) insn
not recognized because fp hasn't been converted yet, and 2) max number
of generated reload insns.
any pointers will be appreciated
shmeel
On 04-Jun-15 03:54 AM, Jim Wilson wrote:
On 06/02/2015 11:39 PM, shmeel gutl wrote:
find_modifiable_mems was introduced to gcc 4.8 in september 2012. Is
there any documentation as to how it is supposed to help the haifa
scheduler?
The patch was submitted here
https://gcc.gnu.org/ml/gcc
find_modifiable_mems was introduced to gcc 4.8 in september 2012. Is
there any documentation as to how it is supposed to help the haifa
scheduler?
In my private port of gcc it make the following type of transformations
from
a= *(b+20)
b+=30
to
b+=30
a=*
On 16-May-15 03:49 PM, Ajit Kumar Agarwal wrote:
if (loop && loop->latch == bb
|| loop->header == bb)
Please add parenthesis to the various occurrences of this code fragment.
Better if the precedence is explicit.
It seems that in gcc 4.7, the rnreg pass for renaming registers after
reload is not vliw aware. In particular I saw it reassign a register
that is in use in the same vliw.
To be more concrete, I saw it change the following pseudo code
DI:a30 = v0
SI:a14 = -a14
to
DI:a30 = v0
SI
On 09-Dec-14 07:56 PM, Jeff Law wrote:
On 12/09/14 10:10, Vladimir Makarov wrote:
generate the correct code in many cases even for x86. Jeff Law tried
IRA coloring reusage too for reload but whole RA became slower (although
he achieved performance improvements on x86).
Right. After IRA was com
On 02-Dec-14 12:23 PM, Richard Biener wrote:
On Tue, Dec 2, 2014 at 12:11 AM, shmeel gutl
wrote:
While testing my implementation of passing arguments in registers, I noticed
that gcc 4.7 creates instruction dependencies when it doesn't have to.
Consider:
int foo(int a1, int a2, int a3, i
It works fine for my test case.
Thanks
Richard Biener wrote:
>On Tue, Dec 2, 2014 at 12:11 AM, shmeel gutl
> wrote:
>> While testing my implementation of passing arguments in registers, I noticed
>> that gcc 4.7 creates instruction dependencies when it doesn't have to.
On 23-May-14 05:20 PM, Vladimir Makarov wrote:
On 2014-05-23, 3:49 AM, shmeel gutl wrote:
On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put
insn2, insn1.
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but
On 23-May-14 01:59 PM, Bernd Schmidt wrote:
On 05/23/2014 10:07 AM, shmeel gutl wrote:
Exposed pipeline is not my problem. Negative latency is my problem. I
don't see negative latency for c6x, not in unit reservations and not in
adjust cost. Did I miss something?
You just need to mod
On 22-May-14 07:21 PM, Bernd Schmidt wrote:
On 05/21/2014 05:30 PM, Vladimir Makarov wrote:
On 2014-05-20, 5:18 PM, shmeel gutl wrote:
The problem that I see is that the haifa scheduler schedules one cycle
at a time, in a forward order, by picking from a list of instructions
that can be
On 21-May-14 06:30 PM, Vladimir Makarov wrote:
I am just curious what happens when you put
insn2, insn1.
and insn2 uses a result of insn1 in 6 cycles and insn1 producing the
result in 3 cycles, but there are not ready functional units (e.g.
arithmentic units) necessary for insn1 for 4 or more
On 20-May-14 06:13 PM, Vladimir Makarov wrote:
On 05/19/2014 02:13 AM, shmeel gutl wrote:
Are there hooks in gcc to deal with negative latencies? In other
words, an architecture that permits an instruction to use a result
from an instruction that will be issued later.
Could you explain more
f Of shmeel
gutl
Sent: Monday, May 19, 2014 12:23 PM
To: Andrew Pinski
Cc: gcc@gcc.gnu.org; Vladimir Makarov
Subject: Re: negative latencies
On 19-May-14 09:39 AM, Andrew Pinski wrote:
On Sun, May 18, 2014 at 11:13 PM, shmeel gutl
wrote:
Are there hooks in gcc to deal with negative latencies
On 19-May-14 09:39 AM, Andrew Pinski wrote:
On Sun, May 18, 2014 at 11:13 PM, shmeel gutl
wrote:
Are there hooks in gcc to deal with negative latencies? In other words, an
architecture that permits an instruction to use a result from an instruction
that will be issued later.
Do you mean
Are there hooks in gcc to deal with negative latencies? In other words,
an architecture that permits an instruction to use a result from an
instruction that will be issued later.
At first glance it seems that it will will break a few things.
1) The definition of dependencies cannot come from th
On 28-Mar-14 01:46 PM, Hannes Frederic Sowa wrote:
On Fri, Mar 28, 2014 at 09:41:41AM +, Andrew Haley wrote:
Ok, I see the problem. Maybe something like this by avoiding the term?
Using this clobber causes the compiler to flush all (modified)
registers being used to store values which gcc d
For the 4.7 branch I only saw one architecture using exposed pipeline.
Is there any documentation on the quality of exposed pipeline support?
Does the back-end need to do anything special to deal with jumps and
returns from calls?
Thanks
Shmeel
On 06-Dec-13 01:34 AM, Maxim Kuvyrkov wrote:
On 6/12/2013, at 8:44 am, shmeel gutl wrote:
On 05-Dec-13 02:39 AM, Maxim Kuvyrkov wrote:
Dependency type plays a role for estimating costs and latencies between
instructions (which affects performance), but using wrong or imprecise
dependency
On 05-Dec-13 02:39 AM, Maxim Kuvyrkov wrote:
Dependency type plays a role for estimating costs and latencies between
instructions (which affects performance), but using wrong or imprecise
dependency type does not affect correctness.
On multi-issue architectures it does make a difference. Anti d
For my VLIW toolchain, I am not allowed to output .loc directives in the
middle of a VLIW bundle. Following the lead of the bfin backend, I scan
bundles during the machine reorg pass and ensure that all of the insns
of a bundle have the same location. This solves most of the problems,
but final
On 09-Aug-13 07:35 PM, Vladimir Makarov wrote:
On 13-08-09 7:25 AM, shmeel gutl wrote:
I am having trouble meeting the constraints of the scheduler and the
register allocator for my back end. The relevant features are:
1) VLIW - up to 4 instructions can be issued each cycle
2) If a vliw
I am having trouble meeting the constraints of the scheduler and the
register allocator for my back end. The relevant features are:
1) VLIW - up to 4 instructions can be issued each cycle
2) If a vliw bundle has both a set and a use, the use will use the old
values.
3) A call instruction will p
The latency calculations in my backend are very complicated. Is there
any automated way to test them?
In the architecture that I am using, there is a big pipeline penalty for
read after write to the same memory location. Is it possible to tell the
difference between a possible memory conflict and a definite memory
conflict?
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