I think:
make check-gcc RUNTESTFLAGS="vect.exp"
is what you're looking for.
Tehila.
[EMAIL PROTECTED] wrote on 28/02/2008 08:32:21:
> Hello all,
> I am studying vectorization in GCC.
> I want to run the test cases given in gcc/gcc/testsuite/gcc.dg/vect
> Any pointer will be of great help for me.
Michael Matz <[EMAIL PROTECTED]> wrote on 31/07/2007 18:05:53:
> Hi,
>
> On Tue, 31 Jul 2007, Daniel Berlin wrote:
>
> > > 2. Store-sinking/load hoisting may have an overhead and may degrade
> > > performance unless the relevant conditional branch gets if-converted.
> >
> > I agree with you for co
"Daniel Berlin" <[EMAIL PROTECTED]> wrote on 31/07/2007 18:00:57:
>
> I agree with you for conditional stores/loads.
Great!
>
> The unconditional store/load stuff, however, is exactly what
> tree-ssa-sink was meant to do, and belongs there (this is #3 above).
> I'm certainly going to fight tooth
Hi,
I'd like to bring up on the list a discussion that a bunch of people (most
of those CC-ed above) started at the GCC Summit:
Lately, there were few efforts, that are not necessarily related to each
other, but are all relevant to if-conversion.
Each of them has its own restriction, like a spec
that option.
(We used "systesim" in the past, in cases we didn't have the target (arch)
machine).
Tehila.
> HTH
>
> regards
> saurabh
>
> On Wed, 2007-06-27 at 00:18 +0300, Tehila Meyzels wrote:
> >
> > AFAIK, if you don't have such machine, you won&#x
Venkatesan Jeevanandam <[EMAIL PROTECTED]> wrote on
26/06/2007 09:26:18:
> Hi,
>
> I have been given a set of cross-compiler binaries (like arch-gcc,
> arch-as, arch-ld, arch-ar, arch-gdb, etc.,).
> How can i test "arch-gcc" cross-compiler binary using GCC testsuite ?
Do you have an access to suc
Hi,
I'd like to get an explanation why ifcvt.c checks whether 1 of the 2
successors of the IF-header block has a stmt that exits from the loop?
Why does it prevent the if-conversion?
I'm referring to the following code:
/* Nor exit the loop. */
if ((then_edge->flags & EDGE_LOOP_EXIT)
||
Andrea Callia D'Iddio wrote on 14/03/2007 12:36:59:
> Hi all,
> first of all i want to thank you for the aid that i have receveid from
> this mailing list. I have another little question:
> if i have a statemente that is an expression, for example x+5 , how
> can i know if the operation is plus (
Andrea Callia D'Iddio wrote on 12/03/2007 16:56:53:
> Hi all,
> i have a very little question for you. I have a basic block and by a
> statement iterator i can obtain a tree structure in the following
> manner:
> tree stmt = bsi_stmt (si);
> I want to use this tree structure to manipulate
Revital Eres wrote on 01/03/2007 10:37:36:
>
> Hello,
>
> I wonder why this order (non-consecutive, decreasing) of Altivec
registers
> was chosen when specifying the allocation order in REG_ALLOC_ORDER.
>
> (taken from rs6000.h)
>
>/* AltiVec registers. */
[EMAIL PROTECTED] wrote on 26/02/2007 10:40:59:
>I am targeting GCC 4.1.1 to a custom RISC processor; which has some vector
>instructions (32 bit vectors). It can perform two 16 bit/ or four 8 bit
>additions, subtractions, multiplications & shift operations
simultaneously.
>I would like to use t
Kai Tietz wrote on 19/02/2007 10:29:13:
> Hi,
>
> May somebody can explain me, the following case. I compiled a
> cross-complier for x86_64-pc-mingw32 and was successful on translare with
> the following build steps:
> 1. configure --target=x86_64-pc-mingw32
> 2. make all-gcc
> 3. make install
[EMAIL PROTECTED] wrote on 18/02/2007 14:16:51:
>
> Hi
>
> I want steps to install gcc
>
You can read all here:
http://gcc.gnu.org/install/
BTW, your question seems to be more related to gcc-help mailing list.
This mailing list is for GCC developers.
Good luck,
Tehila.
> thank
>
>
>
> Eng.Mo
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