Hans-Peter Nilsson wrote:
> On Thu, 16 Feb 2006, Sylvain Munaut wrote:
>
>>Move/Load/Store without flag is no problem. But for add, to allow
>>multiword add, carry is needed and I can't make it optionnal.
>
>
> As I hinted, perhaps you can have the multiword
Hans-Peter Nilsson wrote:
> On Wed, 15 Feb 2006, DJ Delorie wrote:
> I wrote:
>
>>>Anyway, at least keep a way to add reg+reg and reg+integer, load and
>>>store of memory and load of integer and address without condition
>>>code effects and your port has a chance to avoid the related bloat.
>>
>
Hans-Peter Nilsson wrote:
> On Wed, 15 Feb 2006, Sylvain Munaut wrote:
>
>> * 2 flags Carry & Zero for testing.
>
>
> I think most of your questions have been answered, so let me
> just add that if nothing else, the port will be much simplified
> if you make
DJ Delorie wrote:
>>So If I use 16 bits registers, do I have to handle pairs of them to form
>>32 bits ?
>
>
> Well, you don't *have* to if your word size is only 16 bits. GCC will
> still pair them, but you'll need to tell gcc how to split them back up
> for the opcodes you have available.
>
>
DJ Delorie wrote:
>> * 8 bit RISC microcontroller
>
> Not 16?
Well, at first it was to save space in the FPGA (basically, the regs and
ALU takes twice the space) and because many 16 bits ops can be done with
8 bits regs and lots of the code I do can live with that.
But I had a quick glance
Hello,
I'm currently considering writing my own microcontroller to use on
a FPGA. Since I'd like to be able to use C to write
"non-timing-critical" parts of my code, I thought I'd include a gcc port
as part of the design considerations.
I've read the online manual about gcc backend and googled
