Hans-Peter Nilsson wrote: > On Wed, 15 Feb 2006, Sylvain Munaut wrote: > >> * 2 flags Carry & Zero for testing. > > > I think most of your questions have been answered, so let me > just add that if nothing else, the port will be much simplified > if you make sure that only specific compare instructions set > condition codes, i.e. not as a nice side-effect of move, add and > sub - or at least make such condition-code side-effects > optional. It depends on too many undisclosed details like > pipeline restrictions to say whether performance is generally > better or worse, but I can tell for sure that the GCC port will > be simpler with a specific set of condition-code setting insns.
Making it optionnal is not hard nor expensive in hardware, the problem is that my opcodes need to be 18 bits and I won't have space to stuff another option bit ... What I was thinking for the moment was to have : - sign is always the msb of the last ALU output - add/sub to modify all flags - move/xor/and/not/or only affect zero (and sign) - shift operations always affect carry and zero - Have some specific instructions like compare and test, but theses would only operate on registers (and not on immediate) What's so bad about have the flag as side-effects ? Here it's a simple MCU, it doesn't have a very long pipeline and that pipeline is 'almost' invisible to the end-user exception for memory fetch and io/access ... > BTW, it depends on the compare (and branch) instructions whether > just two flags are sufficient. g Adding Sign and overflow is pretty easy. And the compare instruction/logic path shouldn't be a problem either. MIPS has no flag ??? how does branching work ? Finally, about immediates, I'm thinking of having instruction like add could have 4 different forms : add rD, rA, rB add rA, rA, imm add rA, rA, imm<<8 add rA, rA, signextend(imm) Is that kind of manipulation on the immediate well understood by gcc internals ? Or maybe just allow immediates in the mov but that seems like a big penalty ... Sylvain
