ify this file and then submit it
> back into gcc for processing to create an executable/assembly dump?
It has been a while since I have worked on GCC - back then (a couple
of years ago) this was not possible. I do not have reason to believe
this would have changed.
Pranav
all DI
> operands are replaced with SI.
>
> I understand that this is a desireable optimzation but then the load
> is done using two load 4 bytes instructions.
>
> Does anybody has any idea what should I do?
Could it be a problem with the constraints in your movdi define_insn ?
Pranav
L dead-store elimination. In my case addr is
based on the stack pointer and the store is to a local variable on the
stack.
Thanks,
Pranav
llowing S1
either. Is the dse pass expected to remove such stores ? (I am
inclined to think that it should, but I am seeing a case where dse
doesnt remove such stores) . Further is the behaviour expected to be
different if the "addr" is based on "fp" ?
TIA,
Pranav
component_ref_for_mem_expr.
> ...
>
> this change.
>
> Richard.
Great. Thanks.
Pranav
Richard,
> If you are not working on trunk this can happen because the way
> MEM_EXPRs are "canonicalized".
Thanks. Yes, I am not on trunk and may not be able to move right away.
I would appreciate some pointers about where I should look, If I want
to fix this ?
Thanks,
Pranav
shy here with the tree node that MEM_EXPR is giving me
?
Thanks,
Pranav
utation, loop fusion / fission, strip mining,
etc in the summers. As I do not know what all optimizations are expected
to be covered in the project could you please help me with the problem
before I write my project proposal.
Thank you.
Regards,
Pranav Garg.
provided your optimization has been correctly
implemented in the context of GCC you should be good to go.
HTH,
Pranav
On Wed, Aug 20, 2008 at 7:45 PM, Rohan Sreeram <[EMAIL PROTECTED]> wrote:
> Hi,
>
> I am a student in Utah State University researching on compilers optimization
&g
u will notice that the scheduler
would have, in all likelihood, accounted for the delay of 1 cycle
between the "lw" and the "add" instructions. Only that you will have
to put the "nop" yourself between these two instructions.
cheers!
Pranav
there something I can do to improve
the case with the "logical and"
May be this is difficult on hardware that uses the CC register ? But I
am working on a private port that doesnt use the CC register.
Thanks,
Pranav
short ione;
short itwo;
short ithree;
short ifour;
short ifive;
int
> Btw, I have a fix.
oh gr8. I just saw your post on the gcc-patches. Do you still want me
to add this to PR35163 for the record ?
Cheers!
Pranav
/35163
* fold-const.c (fold_widened_comparison): Use get_unwidened in
value-preserving mode. Disallow final truncation.
Now with the patch reverted, test.c.003t.original has
fail = (int) ssi >= (int) usi;
And this problem vanished.
Am I missing something here ?
Thanks,
Pranav
int fa
2.
My question is, shouldnt scalar evolution ignore PHI nodes with one
argument (implying a copy) or If not atleast pay heed to the cost of
additional computations introduced.
cheers!
Pranav
software. We
implemented this for the TMS320C6x VLIW DSP.
HTH,
Pranav
ever, for c6x-gcc the reason cc1 doesnt allocate
functional units is that the assembler ( as part of the c6x binutils )
does the functional unit allocation on its own. There are some notes
about how the assembler does this in Extending the GNU Assembler for
Texas Instruments TMS320C6x-DSP.pdf
HTH,
Pranav
>
> Regards,
> Li Wang
>
USAGE, which are
> always correct, so a solution to your problem would be to scan it for uses of
> registers in caller-save.c:insert_one_insn. Of course this wouldn't plug the
> hole entirely but would very likely be sufficient in practice.
Good idea, I'll try using CALL_INSN_FUNCTION_USAGE.
cheers!
Pranav
er Write). Shouldnt regs in
REG_DEP_TRUE be added to
live_throughout. My suspicion is that the LOG_LINKS are not always
up-to-date, therefore will it be
better to use DF_INSN_UID_USES ?
Thanks in advance,
Pranav
(reg:SI 1 $c1 [ ivtmp.101 ]))
(nil))
TIA,
Pranav
> Did you test for large programs? Such as applications from SPEC 2006? or
> the equal size of programs. Thanks.
Oh no, we didnt. We stopped when we achieved fair stability purely on
the basis of
the number of testsuite failures ( less than 100).
cheers!
Pranav
ecked for
> attributes using the RTX of the operand. We were unable to get any
> information from other target specific attributes.
Look up MEM_EXPR in the internals. You might want to use that for the
register indirect
case.
cheers!
Pranav
mpiler - rev 129547,
DATESTAMP 20071022.
cheers!
Pranav
y then ( about 3 years back).
- Pranav
had added some
improvements to this port as part of
undergraduate university coursework ( project).
cheers!
Pranav
e from
reload_inmode or reload_outmode. */
I am confused whether reg_rtx should always be the rtl expression for
regno ? or am I missing something here.
Anyways shouldnt reload be checking for live registers before
reloading into them ?
TIA,
Pranav
= Hoopster_ptr_17->Magic;
gets changed to
D.1281_6 = MEM[index: ivtmp.840_5];
I am wondering If increasing OP_SIZE_{1,2,3} is the way to go. Partly
not convinced because it means that the problem could hit again with
nastier code.
TIA,
Pranav
testcase-min.i
Description: Binary data
testc
REGATE_TYPE_P trees.
Aha, this would be neater.
Thanks for pointing me in the right direction.
cheers!
Pranav
tags can never have subvars. */
if (!DECL_P (v) || MTAG_P (v))
return false;
Am I missing something here ?
TIA,
Pranav
able the scheduling for that particular dependency, or
> (2) Inform GCC that "movpqi_insn" has an additional dependency in AR15
>
> The problem is, I still don't know how can i do those 2 things ... So if any
> of you have any advice, I'd be really grateful :D
Ideally you could either split movpqi_insn (into a store and a load)
during expansion or split the insn appropriately just before
instruction scheduling (using a define_insn_and_split) .
cheers!
Pranav
Hi,
> Pranav, although there is indeed a bug in the mid-end here, from your point
> of view the simple and effective workaround should be to implement a movdi
> pattern (and movsf and movdf if you don't have them yet: it's an absolute
> requirement to implement movMM fo
t_int 1 [0x1])
(insn_list:REG_RETVAL 14 (expr_list:REG_EQUAL (float:SF (reg:SI 138))
(nil)
The answer to this question will help me decide where to fix the
problem, In the expander itself or while processing REG_EQUAL in the
cse pass.
Thanks,
Pranav
SI 140)
(const_int -2147483648 [0x8000])) 44 {*movsi} (nil))
Thanks,
Pranav
nary_operation_1 in simplify-rtx.c tries to
/* Canonicalize XOR of the most significant bit to PLUS. */
(simplify-rtx.c:2203)
and this results in a PLUS on CONST_INT and CONST_DOUBLE.
maybe there should be a better check before canonicalizing here ?
Thanks,
Pranav
n calls CONST_DOUBLE_LOW.
Thanks,
Pranav
my backend (
as in will I need to define movsf in my backend, which isnt defined at
present ) ?
Regret the rather verbose post.
Thanks in advance,
Pranav
Hi,
> Or perhaps this could be another manifestation of the "cse gets confused by
> reg_equal notes on subparts of dimode pseudos if no movdi pattern is defined
> in the backend" bug[*]? Pranav, is there a movdi pattern in your backend?
> There needs to be one, gcc do
at case. It may be that
> remove_retval_note needs to look for and remove a REG_EQUAL note.
Ok, so the approach should be to fix remove_retval_note to have it
remove REG_EQUAL note too rather than not call remote_retval_note at
all. I will submit a patch for comments.
Thanks,
Pranav
should
be careful when REG_RETVAL and REG_EQUAL appear in the same insn. Is
this the right way of going about it ?
Sorry for a rather verbose post.
Thanks in advance,
Pranav
erefore you will need to write a .exp file ( e.g arm-sim.exp) file
and put it in the dejagnu/baseboards directory. Then while doing make
check-gcc pass it using the RUNTESTLFAG command line argument.
Typically,
$> make check-gcc RUNTESTFLAGS="--target_board=-sim"
HTH,
Pranav
md file) and then try to check the reason
for recog crashing. IMO, the predicate may not be passing.
regards,
Pranav
marker (or maybe "-O2
-fno-wrapv")? But your optimization should also be conditional on
whether strict overflow behavior is requested.
Paolo
Thanks, I will prepare a patch. A 'strict overflow behaviour' check
also makes sense.
Thank you,
Pranav
ys returns
1 and the testcase fails.
My question is that, IMO the test is checking overflow behaviour. Is
it right to have such a test ?
Regards,
Pranav
?
Am I missing something here ?
TIA,
Pranav
d after every 'ashift' whereas
we are interested only in the lower order 8 bits. However when i try
the same thing with int instead of char i.e. there is no need for
extension then the operations get converted into b<<=3 instead of 3
instructions.
regards,
Pranav
and realised
that we need an instruction that does a zero extend before a store so
that that the extension instructions become redundant and can be
removed.
Thank you,
Pranav
Also this is removed for the case of integers by the CSE pass
IIRC . The problem arises only for the type being a char or a short.
Yes, That is true. With gcc 4.1 one of the 'or's gets eliminated for
'int'. I am putting below two sets of logs. The first just before
cse_main and the second just a
om the documentation, the
prototypes of all the functions in the source file i.e. the
.c file should go into -protos.h
HTH,
Pranav
little endian or not, sizes of integral
types etc.
The file .c, like you rightly said defines the targetm
structure that holds pointers to target related functions and data.
Such functions are defined in the .c file. Such target hooks are
#defined in the .c file.
HTH,
Pranav
On 1/15/07, Richard Guenther <[EMAIL PROTECTED]> wrote:
On 1/15/07, pranav bhandarkar <[EMAIL PROTECTED]> wrote:
> Hello Everyone,
> I have the following source code
>
> static int i;
> static char a;
>
> char foo_gen(int);
> void foo_assert(char);
> v
ior operation is immediately
copied into memory. I am compiling this case with -O3. Can anybody
please tell me how this problem can be overcome.
TIA,
Pranav
anybody please help me out.
Thanks in advance,
Pranav
--
"So far as I am able to judge, nothing has been left undone,
either by man or nature, to make India the most extraordinary
country that the sun visits on his rounds. Nothing seems to
have been forgotten, nothing overlooked."
Mark Twain
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