pre_modify/post_modify with scaled register

Hi, The gccint docs for pre_modify/post_modify say that the address modifier must be one of three forms: (plus:m x z), (minus:m x z), or (plus:m x i), where z is an index register and i is a constant. Why isn’t (plus:m x (mult:m z i)) supported, for architectures that support scaling of the inde

LRA - insn does not satisty its constraints

Hi, I've been looking at updating some of the targets to use LRA. On some targets that have a one register & immediate instruction format (i.e. dest register and source register are the same), I see errors such as: error: insn does not satisfy its constraints: (insn 2 7 5 2 (set (reg/f:SI 12 r12

RE: Double word left shift optimisation

> This is interesting. I've quickly tried it out on the SH port. It can be > accomplished with the combine pass, although there are a few things that > should be taken care of: > - an "extendsidi2" pattern is required (so that the extension is not > performed before expand) > ... > One potentia

Double word left shift optimisation

Hi, I'd like to try to optimise double word left shifts of sign/zero extended operands if a widening multiply instruction is available. For the following code: long long f(long a, long b) { return (long long)a << b; } ARM, MIPS etc expand to a fairly long sequenc

RE: Integer promotion for register based arguments

Hi Eric, > > I guess my question is what would I need to change to make it work > > like the ARM port? I can't see how this is being controlled. > > Try TARGET_PROMOTE_PROTOTYPES. Thanks, actually it does turn out to be this, but I was confused by the documentation. If this returns true, I see s

RE: Identifying Compiler Options to Minimize Energy Consumption by Embedded Programs

Hi James, > - Which set of benchmarks are suitable for embedded applications and representative of possible applications? Have a look at CoreMark: http://www.coremark.org/ EEMBC also have EnergyBench: http://www.eembc.org/benchmark/power_sl.php although I think that might be commercial, but it

RE: Integer promotion for register based arguments

Hi Eric, > > I guess my question is what would I need to change to make it work > > like the ARM port? I can't see how this is being controlled. > > Try TARGET_PROMOTE_PROTOTYPES. For all 3 targets I believe this returns true (Both MIPS and LM32 use hook_bool_const_tree_true), so I presume it m

RE: Integer promotion for register based arguments

Hi Andrew, > On 07/25/2012 12:15 PM, Jon Beniston wrote: > > For MIPS and LM32, truncation is performed in the calling function and > > sign extension in the called function. One of these operations seems > > redundant. For ARM, truncation is performed in the caller, but >

Integer promotion for register based arguments

Hi, I've tried compiling the following program targeting both MIPS, LM32 and ARM. long a, b; void func(short p) { b = (long)p; } int main() { if(a < 2) func((short)a); return 0; } For MIPS and LM32, truncation is performed in the calling function and sig

RE: Bug in expand_builtin_setjmp_receiver ?

Hi Fred, > If you have access to a lm32 toolchain, can you test if gcc.c- > torture/execute/built-in-setjmp.c passes at different optimization levels? For a SVN snapshot from yesterday, patched so it fixes the problem Nathan mentioned: FAIL: gcc.c-torture/execute/built-in-setjmp.c execution, -

Re: Bug in expand_builtin_setjmp_receiver ?

Hi Nathan, > lm32 has a gdb simulator available, so it should be fairly easy to write > a board file for it if one doesn't already exist. > > Unfortunately, building lm32-elf is broken in several different ways > right now. What problems do you have building lm32-elf? If you let me know, I can t

RE: Updating multilib support after a compiler is built

Thanks for the suggestions. > If you only want to optimize some libraries but not others, GCC doesn't > effectively support different multilibs having different sets of libraries either. > My proposal > would have the effect of making it much easie

Updating multilib support after a compiler is built

Hi, Is it possible to update the multilib combinations supported by GCC after it has been built? (I would like to build some libraries optimised for different CPUs variants, that aren't built by default). I tried doing this via a specs file, but something like the following fails: %rename multil

RE: Lattice Mico32 port

> The port is ok to check in. Great - so can I apply it, or does someone else need to? Cheers, Jon

RE: VOIDmode in ZERO_EXTEND crashed

> PS: Does gcc have a function which could dump the specified rtx? > I wanna dump the rtx when the crash happening. debug_rtx(x); You can also call this from within GDB, by typing: call debug_rtx(x) Cheers, Jon

RE: Lattice Mico32 port

Hi Richard, >> Index: gcc/config/lm32/sfp-machine.h >> Index: gcc/config/lm32/crti.S >> Index: gcc/config/lm32/lib1funcs.S >> Index: gcc/config/lm32/crtn.S >> Index: gcc/config/lm32/arithmetic.c >> Index: gcc/config/lm32/t-fprules-softfp >> Index: gcc/config/lm32/t-lm32 > >Can you move these to li

Array alignment difference on stack

Hi, With a port of GCC 4.2.1 I'm working on, get_pointer_alignment() (via DECL_ALIGN) returns different values for a char array depending upon whether it is on the stack or not. For example, if the array is a global, get_pointer_alignment() always returns 32, regardless, if there are more than 4

RE: Inline memcpy in GCC 4.1.1

> > In http://gcc.gnu.org/ml/gcc/2006-06/msg00185.html, your wrote: > > > So, two questions: any idea why 4.1.1 is no longer able to > > automatically inline memcpys and why is the source operand for > > movmemsi not know to be as widely aligned as it actually is? > > See PR middle-end/27226 >

Inline memcpy in GCC 4.1.1

Hi, I'm updating a port from 3.4.6 to 4.1.1. In 3.4.6, I hadn't implemented movmemsi patterns, but the compiler could still inline memcpy's (and also strcpys where source string is a const) by itself. After updating to 4.1.1, calls to memcpy are always generated. I've had a bash at implementing

RE: Store scheduling with DFA scheduler

Hi Vlad, > There is not enough information to say what is wrong. It > would be better if you send gcc output when > -fsched-verbose=10 is used. Cheers, Jon ;; == ;; -- basic block 0 from 18 to 32 -- before reload ;; ==

RE: Store scheduling with DFA scheduler

> Jon, > > (define_insn_reservation "arith" 1 (eq_attr "type" "arith") "x") > > (define_insn_reservation "loads" 2 (eq_attr "type" "load") "x,m") > > (define_insn_reservation "stores" 3 (eq_attr "type" > "store") "x,m*2") > > Stores don't really have a 'result', why have you set the > cycle c

Side-effect latency in DFA scheduler

Hi, How is the latency of instructions that have side effects modeled in the DFA scheduler. For example, define_insn_reservation only has one latency value, yet instructions such as loads with post increment addressing have two outputs, possibly with different latencies. Do both outputs get the sa

Store scheduling with DFA scheduler

Hi, I'm trying to get the DFA scheduler in GCC 4.0.0 to schedule loads and stores, but I can only get it to work for loads. I have an automaton defined as follows: (define_automaton "cpu") (define_cpu_unit "x" "cpu") (define_cpu_unit "m" "cpu") (define_insn_reservation "arith" 1 (eq_attr "type"

RE: Register allocation in GCC 4

Hi Nathan, > I guess > it must be to do with function calling Good call. I screwed up the conversion from FUNCTION_ARG_PARTIAL_NREGS to TARGET_ARG_PARTIAL_BYTES. Cheers, Jon

Register allocation in GCC 4

Hi, I'm updating a GCC port to 4.0.0. I am seeing a problem whereby registers that are set to 1 in fixed_regs are being used. The problem is occuring quite early on in the compiler, as the registers appear in the 00.expand dump. The problem seems to occur for a DCmode value that is being allocated