> From: Andrew Haley
> To: Jamie Prescott
> Cc: Adam Nemet ; "gcc-h...@gcc.gnu.org"
>
> Sent: Thursday, May 28, 2009 11:48:30 AM
> Subject: Re: Forgetting return values
>
> Jamie Prescott wrote:
> >> From: Adam Nemet
>
> >>>
> From: Adam Nemet
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 28, 2009 11:10:49 AM
> Subject: Re: Forgetting return values
>
> Jamie Prescott writes:
> > static inline int set_prop(char const *path, char const *name,
> >
What am I missing?
I have a simple:
static inline int set_prop(char const *path, char const *name,
void const *data, int size)
{
int error;
asm volatile ("int\t11\n\t"
: "=a0" (error): "a0" (path), "a1" (name), "a2"
> From: Georg-Johann Lay
> To: Jamie Prescott
> Cc: Eric Botcazou ; gcc@gcc.gnu.org; Jim Wilson
> ; Ian Lance Taylor
> Sent: Wednesday, May 27, 2009 12:11:08 PM
> Subject: Re: Seeking suggestion
>
> Jamie Prescott schrieb:
>
> >>> Thanks for the ex
> From: Eric Botcazou
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org; Jim Wilson ; Georg-Johann Lay
> ; Ian Lance Taylor
> Sent: Wednesday, May 27, 2009 10:37:24 AM
> Subject: Re: Seeking suggestion
>
> > Thanks for the explanation. I somehow thought that every insn sp
> From: Jamie Prescott
> To: Jim Wilson
> Cc: Georg-Johann Lay ; Ian Lance Taylor ;
> gcc@gcc.gnu.org
> Sent: Wednesday, May 27, 2009 10:12:42 AM
> Subject: Re: Seeking suggestion
>
> Thanks for the explanation. I somehow thought that every insn spit out by a
> defi
> From: Jim Wilson
> To: Jamie Prescott
> Cc: Georg-Johann Lay ; Ian Lance Taylor ;
> gcc@gcc.gnu.org
> Sent: Tuesday, May 26, 2009 7:47:45 PM
> Subject: Re: Seeking suggestion
>
> Jamie Prescott wrote:
> > Is there a reason why something like this would not
> From: Michael Meissner
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Sunday, May 24, 2009 1:57:19 PM
> Subject: Re: Seeking suggestion
>
> One way is to use match_scratch, and different register classes for the two
> cases.
>
> (define_insn "
> From: Georg-Johann Lay
> To: Jamie Prescott
> Cc: Ian Lance Taylor ; gcc@gcc.gnu.org
> Sent: Saturday, May 23, 2009 12:05:09 AM
> Subject: Re: Seeking suggestion
>
> Jamie Prescott schrieb:
>
> > Is the implementation I posted the only one, or there are shor
> From: Ian Lance Taylor
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Friday, May 22, 2009 5:45:21 PM
> Subject: Re: Seeking suggestion
>
> Jamie Prescott writes:
>
> > But now I get and invalid rtx sharing from the push/pop parallels:
>
> This nor
> From: Jamie Prescott
> To: gcc@gcc.gnu.org
> Sent: Friday, May 22, 2009 10:36:47 AM
> Subject: Seeking suggestion
>
>
> Suppose you're writing the backend for a VM supporting two architectures, in
> which
> one of them clobbers the CC registers for certain
Suppose you're writing the backend for a VM supporting two architectures, in
which
one of them clobbers the CC registers for certain instructions, while the other
does not.
The instructions themselves are exactly the same.
What is the best/shortest/more-elegant way to write this, possibly w/out
> From: Andrew Pinski
> To: Jamie Prescott
> Cc: Ian Lance Taylor ; gcc@gcc.gnu.org
> Sent: Thursday, May 21, 2009 8:22:00 AM
> Subject: Re: nops
>
> On Thu, May 21, 2009 at 8:13 AM, Jamie Prescott wrote:
> > My target does not have anything special WRT alignment.
- Original Message
> From: Ian Lance Taylor
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Wednesday, May 20, 2009 9:50:50 PM
> Subject: Re: nops
>
> Jamie Prescott writes:
>
> > Under which conditions GCC generates nops?
>
> It depends entir
Under which conditions GCC generates nops?
I noticed that with 4.4.0, gen_nop() is required, thing that wasn't with 4.3.3.
Can I just define an empty insn for nop, of GCC requires a one-byte insn for its
own alignment purposes?
- Jamie
> From: Andrew Pinski
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Saturday, May 16, 2009 8:04:59 AM
> Subject: Re: Extending constraints using register subclasses
>
> On Sat, May 16, 2009 at 7:57 AM, Jamie Prescott wrote:
> > Now I managed to have the
> From: Andrew Pinski
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Monday, May 11, 2009 4:47:57 PM
> Subject: Re: Extending constraints using register subclasses
>
> On Mon, May 11, 2009 at 4:45 PM, Jamie Prescott wrote:
> >
> > Hi!
> > I
> From: Jamie Prescott
> To: gcc@gcc.gnu.org
> Sent: Friday, May 15, 2009 3:28:18 PM
> Subject: Different reload behavior from 4.3.3 to 4.4
>
>
> In my VM, the X_REGS class is a generic 64bit regsiter class that can hold
> both 64bit DImode and 64bit DFmode.
> Such
> From: Jamie Prescott
> To: gcc@gcc.gnu.org
> Sent: Friday, May 15, 2009 4:16:30 PM
> Subject: Re: Different reload behavior from 4.3.3 to 4.4
>
>
> > From: Jamie Prescott
> > To: gcc@gcc.gnu.org
> > Sent: Friday, May 15, 2009 3:28:18 PM
> > Subjec
> From: Jamie Prescott
> To: gcc@gcc.gnu.org
> Sent: Friday, May 15, 2009 3:28:18 PM
> Subject: Different reload behavior from 4.3.3 to 4.4
>
>
> In my VM, the X_REGS class is a generic 64bit regsiter class that can hold
> both 64bit DImode and 64bit DFmode.
> Such
In my VM, the X_REGS class is a generic 64bit regsiter class that can hold
both 64bit DImode and 64bit DFmode.
Such class does not allow direct constant loading, so in 4.3.3 I had:
enum reg_class
xxx_preferred_reload_class(rtx x, enum reg_class regclass)
{
enum machine_mode mode = GET_MOD
> From: Diego Novillo
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Friday, May 15, 2009 2:40:15 PM
> Subject: Re: 4.4 API changes
>
> On Fri, May 15, 2009 at 17:23, Jamie Prescott wrote:
>
> > I managed to migrate my code to 4.4, but I've some
> From: Diego Novillo
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Friday, May 15, 2009 2:44:23 PM
> Subject: Re: Writing over [SP]
>
> On Thu, May 14, 2009 at 18:18, Jamie Prescott wrote:
> >
> > This is driving me crazy. Any memory op th
I managed to migrate my code to 4.4, but I've some code I cannot figure out
how to translate.
Before, I was building the TRUE and FALSE instruction list using
gimplify_and_add(),
and then a:
build3(COND_EXPR, void_type_node, cond, a_case, b_case);
Where 'a_case' and 'b_case' were tree's.
Now I
- Original Message
> From: Ian Lance Taylor
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 10:09:40 PM
> Subject: Re: Compact regsiter allocation
>
> Jamie Prescott writes:
>
> > If not, what is the best spot (in the norma
> From: Ian Lance Taylor
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 10:09:40 PM
> Subject: Re: Compact regsiter allocation
>
> Jamie Prescott writes:
>
> >> Normally gcc will allocate registers in the order they are list
- Original Message
> From: Ian Lance Taylor
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 8:57:08 PM
> Subject: Re: Compact regsiter allocation
>
> Jamie Prescott writes:
>
> > The VM I'm retargeting GCC to, has an in
The VM I'm retargeting GCC to, has an instruction that allows to store/load
multiple,
a consecutive range of registers, to a memory operand.
I noticed that sometime the registers allocated by GCC are sparse, and this
prevents
the store/load multiple optimization from happening (I have to issue s
- Original Message
> From: Jamie Prescott
> To: Jamie Prescott ; Michael Meissner
>
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 5:36:14 PM
> Subject: Re: Extending constraints using register subclasses
>
> - Original Message
> > From: J
- Original Message
> From: Jamie Prescott
> To: Michael Meissner
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 4:22:13 PM
> Subject: Re: Extending constraints using register subclasses
> OK, I tried reordering the classes by putting smaller ones first. Did not
- Original Message
> From: Michael Meissner
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 11:38:18 AM
> Subject: Re: Extending constraints using register subclasses
>
> On Mon, May 11, 2009 at 04:45:26PM -0700, Jamie Prescott wrot
This is driving me crazy. Any memory op that tries to write over [SP] get's
automatically nuked
by the compiler.
Any offset, positive or negative, from SP, has no problems.
What did I do wrong this time?
- Jamie
- Original Message
> From: Michael Meissner
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 11:38:18 AM
> Subject: Re: Extending constraints using register subclasses
>
> On Mon, May 11, 2009 at 04:45:26PM -0700, Jamie Prescott wrot
- Original Message
> From: Jim Wilson
> To: Jamie Prescott
> Cc: Paolo Bonzini ; gcc@gcc.gnu.org
> Sent: Wednesday, May 13, 2009 6:15:07 PM
> Subject: Re: Code generation problem with optimizations enabled
>
> Jamie Prescott wrote:
> > Thank you Paolo, I&#
> >> On Mon, May 11, 2009 at 4:45 PM, Jamie Prescott wrote:
> >>
> >>> Hi!
> >>> I wanted to add finer (one per) register subclasses, so that I can more
> finely
> >> control
> >>> the register placement inside the inline a
- Original Message
> From: Paolo Bonzini
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Tuesday, May 12, 2009 1:31:53 AM
> Subject: Re: Code generation problem with optimizations enabled
>
> > What I noticed is that if I CC_STATUS_INIT (in xxx_notice_updat
Thank you Paolo, I'll take a look at it.
Is there a reason why the fcmp insn was dropped with such implementation?
- Jamie
- Original Message
> From: Paolo Bonzini
> To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Tuesday, May 12, 2009 1:31:53 AM
> Subject:
- Original Message
> From: Jamie Prescott
> To: gcc@gcc.gnu.org
> Sent: Monday, May 11, 2009 11:59:23 PM
> Subject: Code generation problem with optimizations enabled
> If I disable the optimizations, everything is fine and the 'fcmp' is there.
> Even wit
Hi!
I have this little code that drives me crazy about the code generation (GCC
4.3.3).
extern double tle_mk_inf(int);
double tle_exp(double dval)
{
if (dval == 0.0)
return 0.0;
if (dval > 1)
return tle_mk_inf(1);
return -1.2;
}
If
; To: Jamie Prescott
> Cc: gcc@gcc.gnu.org
> Sent: Monday, May 11, 2009 4:47:57 PM
> Subject: Re: Extending constraints using register subclasses
>
> On Mon, May 11, 2009 at 4:45 PM, Jamie Prescott wrote:
> >
> > Hi!
> > I wanted to add finer (one per) register subclasse
Hi!
I wanted to add finer (one per) register subclasses, so that I can more finely
control
the register placement inside the inline assembly.
These are the relevant definitions inside my include file:
enum reg_class
{
NO_REGS = 0,
GENERAL_REGS,
X_REGS,
R0_REG, R1_
Never mind, setting STRICT_ALIGNMENT to zero did the trick.
- Jamie
- Original Message
> From: Jamie Prescott
> To: gcc@gcc.gnu.org
> Sent: Saturday, May 9, 2009 1:20:28 PM
> Subject: Avoid subreg access patterns
>
>
> Sorry for the newbie question, bu
Sorry for the newbie question, but I don't seem to get around it.
The backend I'm writing has 32 bit registers, and 64 bit registers (used for
SF, DF, DI).
There is a direct store instruction from a 64 bit register, to memory, and this
instruction is correctly
seen and used by GCC in other occas
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