----- Original Message ----
> From: Ian Lance Taylor <i...@google.com>
> To: Jamie Prescott <jpre...@yahoo.com>
> Cc: gcc@gcc.gnu.org
> Sent: Thursday, May 14, 2009 8:57:08 PM
> Subject: Re: Compact regsiter allocation
>
> Jamie Prescott writes:
>
> > The VM I'm retargeting GCC to, has an instruction that allows to store/load
> multiple,
> > a consecutive range of registers, to a memory operand.
> > I noticed that sometime the registers allocated by GCC are sparse, and this
> prevents
> > the store/load multiple optimization from happening (I have to issue single
> push/pop).
> > Is it possible in some way to instruct GCC to make the allocation compact?
> > So, for example, instead of allocating r8, r10, r12 and r15, allocate
> > r8..r11?
>
> Normally gcc will allocate registers in the order they are listed in
> REG_ALLOC_ORDER, which defaults to increasing numeric order. gcc won't
> normally allocate register sparsely. That said, it is quite possible
> for gcc to allocate a register and then discover that it need not be
> allocated. There isn't currently any way to request that gcc tighten up
> the register allocation. That would probably require another
> optimization pass to consistently rename registers when there is a hole
> in the allocation order.
Yep, usually it allocates compact, but I noticed that when there's some inline
assembly
with ad-hoc register naming, it starts generating holes.
The extra renaming pass, is it something available today?
If not, what is the best spot (in the normal GCC target hooks) to trigger it?
Where the
full insn tree is passed in such hook (if it's not a global)?
- Jamie
