expr.c line 8139 has this:
/* Attempt to return something suitable for generating an
indexed address, for machines that support that. */
if (modifier == EXPAND_SUM && mode == ptr_mode
&& host_integerp (treeop1, 0))
{
tree exp1 = treeop1;
Snapshot gcc-4.4-20110823 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.4-20110823/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.4 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches
On 08/23/2011 07:01 PM, omall...@msu.edu wrote:
Quoting Gordan Bobic :
Unfortunately there is no way I could make it, but on the subject of 3D
support on ARM, Luke recently mentioned something that initially seemed
outlandish but upon closer examination doesn't seem like a bad idea. As
we all kn
On 08/23/2011 01:41 PM, Konstantin Vladimirov wrote:
> Yes, it is exactly what I have now -- myself optimization pass with
> peephole-like rule for such cases. Is it all, that is possible here?
Certainly you can do more than peepholes. That's why I told you to
look at compare-optimize.c.
> May b
On Tue, Aug 23, 2011 at 12:32 PM, Richard Henderson wrote:
> On 08/23/2011 12:18 PM, Konstantin Vladimirov wrote:
>> Hi,
>>
>> Register may at the same time hold data and flags for branch, and live
>> range for data and for flags may be different -- they are totally
>> unrelated. Yes, I allowed mo
Hi,
Lately, I've been trying to get a full libiconv/GMP/MPFR/MPC/PPL/CLooG
GCC build working.
>From vanilla 4.5/4.6/trunk sources, I got the libiconv/GMP/MPFR/MPC
combination to work.
With the patches attached to:
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=50139
I got all the prerequisite libra
On Thu, Aug 18, 2011 at 03:37:15PM +0200, Michael Matz wrote:
> On Wed, 17 Aug 2011, Jed Davis wrote:
>
> > One thing I'm not so sure about is accepting any SYMBOLIC_CONST as a
> > legitimate address. That allows, for example, a symbol address cast
> > to uintptr_t and added to (6ULL << 32), whic
On 08/23/2011 11:37 AM, Konstantin Vladimirov wrote:
> Hi, all
>
> Consider architecture, where *any* data register have associated flag
> field. I.e. any register may be used as a data store to further use,
> and as a flag keeper to further branch.
I don't understand what you mean by "data store
Partial register stall happens when there is a 32bit register read
followed by a partial register write. In your case, the stall probably
happens in the next iteration when 'add eax, 0Ah' executes, so your
manual patch does not work. Try change
add al, [dx] into two instructions (assuming esi is
Hi, all
Consider architecture, where *any* data register have associated flag
field. I.e. any register may be used as a data store to further use,
and as a flag keeper to further branch. Do you have any ideas how to
utilize this property in GCC machine description? May be any examples
of existing
Quoting Gordan Bobic :
Unfortunately there is no way I could make it, but on the subject of 3D
support on ARM, Luke recently mentioned something that initially seemed
outlandish but upon closer examination doesn't seem like a bad idea. As
we all know, the state of openness of specifications o
Hey Andrew,
On 2011/8/22 18:37, Andrew Pinski wrote:
On Mon, Aug 22, 2011 at 6:34 PM, Oleg Smolsky wrote:
On 2011/8/22 18:09, Oleg Smolsky wrote:
Both compilers fully inline the templated function and the emitted code
looks very similar. I am puzzled as to why one of these loops is
significan
On Tue, 23 Aug 2011 17:11:34 +0100, Steve McIntyre
wrote:
On Tue, Aug 09, 2011 at 07:15:34PM +0100, Steve McIntyre wrote:
Hi folks,
Following on from the founding of the cross-distro ARM mailing list,
I'd like to propose an ARM summit at this year's Linux Plumbers
conference [1]. I'm hoping fo
On Tue, Aug 09, 2011 at 07:15:34PM +0100, Steve McIntyre wrote:
>Hi folks,
>
>Following on from the founding of the cross-distro ARM mailing list,
>I'd like to propose an ARM summit at this year's Linux Plumbers
>conference [1]. I'm hoping for a slot on Thursday evening, but this
>remains to be con
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