On Tue, Aug 23, 2011 at 12:32 PM, Richard Henderson <r...@redhat.com> wrote: > On 08/23/2011 12:18 PM, Konstantin Vladimirov wrote: >> Hi, >> >> Register may at the same time hold data and flags for branch, and live >> range for data and for flags may be different -- they are totally >> unrelated. Yes, I allowed mode, but for instance: >> >> and r2, r3, r4 >> sub r5, r2, 0 // <-- this one is excessive, and has already formed flags on >> r2 >> r5.EQ brn LC_0 >> >> may be replaced with >> >> and r2, r3, r4 >> r2.EQ brn LC_0 >> >> But: r5 is from (reg:CC 75) and r2 is from (reg:SI 68). How to have >> register with both flags and data? > > You can't. This will require a port-specific optimization pass. > > You should probably model this simply with CCmode prior to reload, > with the destination as any general register. The example above > would look like: > > (set (reg:si 2) (and:si (reg:si 3) (reg:si 4))) > > (set (reg:cc 5) (compare:cc (reg:si 2) (const_int 0))) > > (set (pc) > (if_then_else (lt (reg:cc 5) (const_int 0)) > (label_ref LC_0) > (pc)))) > > before your new optimization pass runs, and > > (set (reg:si 2) (and:si (reg:si 3) (reg:si 4))) > > (set (pc) > (if_then_else (lt (reg:cc 2) (const_int 0)) > (label_ref LC_0) > (pc)))) > > afterward. > > Your new optimization pass would run during md_reorg, and would > be similar to, but not exactly like, the compare-optimize.c pass. > You would look at the sources to the compare and would backtrack > to see if a compatible set of flags exists elsewhere. > > > r~ >
Hi, Yes, it is exactly what I have now -- myself optimization pass with peephole-like rule for such cases. Is it all, that is possible here? May be I can somehow introduce "mixed" mode? What amount of changes may be required for that? --- With best regards, Konstantin
