> We submitted 2 proposals for 2008 gcc summit. We got one reply
> for one proposal on Mar. 15. But we haven't heard anything on
> the other. April 1 is the deadline for paper if proposal is
> accepted. Today is Mar. 20. I was wondering if anyone on
> gcc mailing list could help us figure out what
On Thu, 20 Mar 2008, Bernd Schmidt wrote:
> Joseph S. Myers wrote:
> > Yes. For SPE, the subregs used in these *frob_* patterns represent concepts
> > including the high-part of a register (only used by certain instructions
> > that treat registers as 64 bits) and a DImode value stored in one 64-
Snapshot gcc-4.3-20080320 is now available on
ftp://gcc.gnu.org/pub/gcc/snapshots/4.3-20080320/
and on various mirrors, see http://gcc.gnu.org/mirrors.html for details.
This snapshot has been generated from the GCC 4.3 SVN branch
with the following options: svn://gcc.gnu.org/svn/gcc/branches
Joseph S. Myers wrote:
Yes. For SPE, the subregs used in these *frob_* patterns represent
concepts including the high-part of a register (only used by certain
instructions that treat registers as 64 bits) and a DImode value stored in
one 64-bit register (normal layout is in two) or a DFmode va
On Thu, 20 Mar 2008, Bernd Schmidt wrote:
> Paolo Bonzini wrote:
> > SPE has patterns for
> >
> > [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
> > (subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
> >
> > for example.
>
> What are they trying to do? It
Paolo Bonzini wrote:
SPE has patterns for
[(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "+r,m")
(subreg:SI (match_operand:SPE64TF 1 "register_operand" "r,r") 4))]
for example.
What are they trying to do? It's dubious for a number of reasons:
- SUBREG in the instruction patter
"Alexey Salmin" <[EMAIL PROTECTED]> writes:
> I want to join the gcc development process and I decided that
> Lexer/cpplib will be a good place to start. It's quite interesting for
> me, I have some experience in this theme in few projects, fortunately
> there is a http://gcc.gnu.org/onlinedocs/cp
Hi all,
I noticed (readelf -lW/grep) that some gcc libraries require executable stack:
/usr/lib64/libffi.so.4.0.1 GNU_STACK 0x00 0x
0x 0x00 0x00 RWE 0x8
/usr/lib64/libgcj.so.8.0.0 GNU_STACK 0x00 0x000
On Mon, Mar 10, 2008 at 03:22:13PM +0300, Sergei Poselenov wrote:
> I've got the ICE on the gcc.c-torture/compile/2718.c test:
> powerpc-linux-gnuspe-gcc -c -O3 -funroll-loops 2718.c
> 2718.c: In function 'baz':
> 2718.c:14: internal compiler error: Segmentation fault
> Please submi
Ross, Christian,
Here are the patches to implement the idea we discussed before. Can you
take a look at it or try it?
http://gcc.gnu.org/ml/gcc-patches/2008-03/msg01200.html
http://gcc.gnu.org/ml/gcc-patches/2008-03/msg01199.html
Thanks - Joey
Joern Rennecke <[EMAIL PROTECTED]> writes:
> On Thu, Mar 20, 2008 at 10:39:47AM +, Richard Sandiford wrote:
>> you're saying that, for any valid values of M and X:
>>
>> (set (subreg:M (reg:N ...) X) (const_int 0))
>>
>> does not guarantee that (subreg:M (reg:N ...) ...) has the value 0
>>
Bernd Schmidt wrote:
Joern Rennecke wrote:
And @code{(subreg:SI (reg:DF 10) 0)} would be a natural way to
express that
you are using the floating point register as a 32 bit integer register,
with writes clobbering the entire 64 bit of the register.
Yes, this is one possible definition. But th
Joern Rennecke wrote:
And @code{(subreg:SI (reg:DF 10) 0)} would be a natural way to express that
you are using the floating point register as a 32 bit integer register,
with writes clobbering the entire 64 bit of the register.
Yes, this is one possible definition. But there's no reason in this
20/3/2008, "Jan Hoogerbrugge" <[EMAIL PROTECTED]> napisał/a:
>Hi,
>
>I am looking for a way to specify that data is not aligned and that therefore
>word accesses should be expanded into byte accesses. For example:
>
>void f(__unaligned int *a)
>{
> *a = 0;
>}
>
>Expands into 4 byte stores. Any su
On Thu, Mar 20, 2008 at 04:27:42PM +0100, Jan Hoogerbrugge wrote:
> Hi,
>
> I am looking for a way to specify that data is not aligned and that therefore
> word accesses should be expanded into byte accesses. For example:
>
> void f(__unaligned int *a)
> {
> *a = 0;
> }
>
> Expands into 4 byte
Hi guys,
I have some weird problem with exception handling on AIX (gcc 3.4.6
with AIX5.3), which I couldn't find any solution for in the web.
-
Problem description:
-
When throwing an exception of some derived object type, catch it,
re-throw
Hi,
I am looking for a way to specify that data is not aligned and that therefore
word accesses should be expanded into byte accesses. For example:
void f(__unaligned int *a)
{
*a = 0;
}
Expands into 4 byte stores. Any suggestions on how to implement this?
Regards,
Jan
Hi,
I am trying to define vec_init. I can only do splats on register
values. So
operands[1] of vec_init should be registers and those registers should
be the same.
Here is some code:
(define_expand "vec_init"
[(match_operand:VEC_MODE32 0 "register_operand" "")
(match_operand 1 "
On 20/03, Arnaud Charlet wrote:
| Maybe that's partly because you are not following closely the development of
| GCC and are not familiar with the GCC stages. Submitting patches during
| stage3 (in particular end of stage3) is not really the most appropriate time,
| so it's often better to wait fo
Hi HJ!
If you look at the website, it says that the paper deadline has been
extended to April 11. It also has abstracts of the accepted talks: if
you submitted a paper and it's not here:
http://www.gccsummit.org/2008/speakers.php?types=TALK
Then I think it's safe to say that it was not accepted
We submitted 2 proposals for 2008 gcc summit. We got one reply
for one proposal on Mar. 15. But we haven't heard anything on
the other. April 1 is the deadline for paper if proposal is
accepted. Today is Mar. 20. I was wondering if anyone on
gcc mailing list could help us figure out what happened t
Hello!
I want to join the gcc development process and I decided that
Lexer/cpplib will be a good place to start. It's quite interesting for
me, I have some experience in this theme in few projects, fortunately
there is a http://gcc.gnu.org/onlinedocs/cppinternals/";>special
manual and http://gcc.gn
> - large merges done in a very short period of time
> - no corresponding test cases or non-regression tests
> - no reference to existing PR
> - no closing of corresponding bugzilla entries
I'm sorry, but that's simply wrong. Test cases are posted, and when suitable,
are added to the test
On 20/03, Arnaud Charlet wrote:
| > Since 2007-12-19, which is the date of the latest AdaCore batch
| > merge (three months ago), the Ada front end has only received the
| > following patches:
| >
| > - platform-specific and build-related patches
| >
| > - gigi (Ada structures -> GCC structu
> Since 2007-12-19, which is the date of the latest AdaCore batch
> merge (three months ago), the Ada front end has only received the
> following patches:
>
> - platform-specific and build-related patches
>
> - gigi (Ada structures -> GCC structures) patches from Éric Botcazou
> in *.c fi
On Thu, Mar 20, 2008 at 10:39:47AM +, Richard Sandiford wrote:
> you're saying that, for any valid values of M and X:
>
> (set (subreg:M (reg:N ...) X) (const_int 0))
>
> does not guarantee that (subreg:M (reg:N ...) ...) has the value 0
> if N is a partial mode?
Yes. Although it will be
> Did you ever get around to looking at my hardware
> interrupt task patch? I know it dates back to Nov/Dec
> but I quite asking about it during stage 2. I submitted
I reviewed it during stage 2 and gave you my comments (the patch was not quite
ready at this time).
> it a couple of times this m
Did you ever get around to looking at my hardware
interrupt task patch? I know it dates back to Nov/Dec
but I quite asking about it during stage 2. I submitted
it a couple of times this month on gcc-patches and
filed this PR so it wouldn't get lost.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=3
> Still no answer after two PING (December and February, for patches
> submitted in November, and there are others not mentionned here). Is
> there any Ada front-end maintainer handling patches proposals?
Yes, as can be seen by other discussions on other patches.
> Since 2007-12-19, which is the
Samuel Tardieu wrote:
> I cannot seem to find an answer to this PING message from last
> December.
>
> > Subject: [PATCH] ada: Do not let a type in an aggregate be an ancestor
> > of itself
> > Date:Thu, 29 Nov 2007 11:43:44 +0100
> > URL: http://gcc.gnu.org/ml/gcc-patches/2007-1
> > I think one reason is that allowing zero_extracts of multi-word modes is
> > (like this subreg thing) a little hard to pin down. What happens when
> > WORDS_BIG_ENDIAN && !BYTES_BIG_ENDIAN
>
> Unless I had my grep wrong, the only such machines to do this are PDP11
> and ARM with special flag
(Yes, the documentation suggests byte_mode for MEMs, but the SH port
uses zero_extracts of SImode MEMs as well, so presumably we're supposed
to support other modes besides the documented ones.)
I think it is just that no one cares about a MEM's mode in this case.
Paolo
Richard Sandiford wrote:
Paolo Bonzini <[EMAIL PROTECTED]> writes:
I think one reason is that allowing zero_extracts of multi-word modes is
(like this subreg thing) a little hard to pin down. What happens when
WORDS_BIG_ENDIAN && !BYTES_BIG_ENDIAN
Unless I had my grep wrong, the only such machi
Paolo Bonzini <[EMAIL PROTECTED]> writes:
>> I think one reason is that allowing zero_extracts of multi-word modes is
>> (like this subreg thing) a little hard to pin down. What happens when
>> WORDS_BIG_ENDIAN && !BYTES_BIG_ENDIAN
>
> Unless I had my grep wrong, the only such machines to do this
Sorry for snipping a lot, but I think the important bit was...
Joern Rennecke <[EMAIL PROTECTED]> writes:
> But the SUBREGS and ZERO_EXTRACTs should still mean the same with respect to
> selecting groups of bits. You simply don't know which of them mean anything
> and what their positional value
I think one reason is that allowing zero_extracts of multi-word modes is
(like this subreg thing) a little hard to pin down. What happens when
WORDS_BIG_ENDIAN && !BYTES_BIG_ENDIAN
Unless I had my grep wrong, the only such machines to do this are PDP11
and ARM with special flags (-mbig-endia
Thanks Mark. I am using classes after they are defined. So it should
be okay for me.
-Doug
2008/3/19 Mark Mitchell <[EMAIL PROTECTED]>:
>
> Doug Kwan (關振德) wrote:
>
> > I have a question about the validity of CLASSTYPE_VBASECLASSES.
> > Due to templates, it is not possible to know if a cla
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