The GICv3 support is used by AArch32 (indicated by the ARM_MULTILIB_ARCH_V4
define) and AArch64 targets. Use the existing WRITE_SR() abstraction to access
the interrupt group 0 and 1 enable registers. This fixes the build for the
AArch32 target.
---
bsps/include/dev/irq/arm-gicv3.h | 23 ++--
On 20.06.22 04:03, chr...@rtems.org wrote:
From: Chris Johns
---
bsps/include/dev/irq/arm-gicv3.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index a79368ebdf..aac02fa191 100644
--- a/bsps/include/dev/irq/arm-gi
On 21.06.22 07:31, Alexandre Oliva via Gcc-patches wrote:
rtems6 declares a global struct bitset in a header file included
indirectly by sys/types.h, that ambiguates the unqualified references
to bitset after "using namespace std" in the testsuite.
Work around the namespace pollution with using
Hello Christian,
On Thu, 2022-06-23 at 18:30 +0200, o...@c-mauderer.de wrote:
> Another tricky part can be how to handle pins or pin groups. At the
> moment I just used an "unsigned" for a single pin. That wouldn't be
> able
> to handle a pin group. Maybe a pin group needs it's own type or some
Hello Duc,
Am 24.06.22 um 16:28 schrieb Duc Doan:
Hello Christian,
On Thu, 2022-06-23 at 18:30 +0200, o...@c-mauderer.de wrote:
Another tricky part can be how to handle pins or pin groups. At the
moment I just used an "unsigned" for a single pin. That wouldn't be
able
to handle a pin group. Ma
