On 20.06.22 04:03, chr...@rtems.org wrote:
From: Chris Johns <chr...@rtems.org>
---
bsps/include/dev/irq/arm-gicv3.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/bsps/include/dev/irq/arm-gicv3.h b/bsps/include/dev/irq/arm-gicv3.h
index a79368ebdf..aac02fa191 100644
--- a/bsps/include/dev/irq/arm-gicv3.h
+++ b/bsps/include/dev/irq/arm-gicv3.h
@@ -335,7 +335,12 @@ static void gicv3_init_cpu_interface(uint32_t cpu_index)
}
/* Enable interrupt groups 0 and 1 */
+#ifdef ARM_MULTILIB_ARCH_V4
+ WRITE_SR(ICC_IGRPEN0, 0x1);
+ WRITE_SR(ICC_IGRPEN1, 0x1);
+#else
gic_icc_write(IGRPEN1, 1);
+#endif
WRITE_SR(ICC_CTLR, 0x0);
}
I have a different patch to fix this:
https://lists.rtems.org/pipermail/devel/2022-June/072056.html
Why was the isb added? Why was the IGRPEN0 write removed in
e70384d3f406251422bac64d11ff44570a678434?
I have to check if the removed ICC_BPR0 is an issue for AArch32.
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