On 3/5/17 4:28 pm, Sebastian Huber wrote:
> On 03/05/17 08:17, Chris Johns wrote:
>> On 3/5/17 3:40 pm, Sebastian Huber wrote:
>>> On 03/05/17 07:28, Chris Johns wrote:
On 3/5/17 3:09 pm, Sebastian Huber wrote:
> On 02/05/17 23:30, Chris Johns wrote:
>> On 2/5/17 6:20 pm, Sebastian Hub
v2 Change Summary (primarily from Chris's feedback):
SLCR:
- Clean up register accesses.
- Add mask for FPGA clock resets.
Device Config:
- Remove DMA buffer static global.
- Remove register map as an argument (only one instance ever).
- Remove bitfile length related code.
- Add bitfile header ch
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c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 5 +
.../libbsp/arm/xilinx-zynq/devcfg/zynq-devcfg.c| 896 +
.../arm/xilinx-zynq/include/zynq-devcfg-regs.h | 197 +
.../libbsp/arm/xilinx-zynq/include/zynq-devcfg.h | 152
c/src/lib/libbsp/arm/xilinx
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c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 5 +
.../arm/xilinx-zynq/include/zynq-slcr-regs.h | 111 +
.../lib/libbsp/arm/xilinx-zynq/include/zynq-slcr.h | 91 +
c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am | 8 ++
c/src/lib/libbsp/
Hi
Has anyone run the whetstone benchmark on real leon3 HW?
I'm almost at 20 minutes of simulated CPU time on tsim so
am suspicious something is wrong.
Any ideas?
--joel
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testsuites/sptests/Makefile.am | 1 +
testsuites/sptests/configure.ac| 1 +
testsuites/sptests/spversion01/Makefile.am | 19 +
testsuites/sptests/spversion01/init.c | 55 ++
testsuites/sptests/spversion01/spversion0
On 03/05/17 22:52, Joel Sherrill wrote:
Has anyone run the whetstone benchmark on real leon3 HW?
I'm almost at 20 minutes of simulated CPU time on tsim so
am suspicious something is wrong.
Any ideas?
Maybe soft-float plus a low CPU frequency? Do you have a function
profiling histogram of the
On 04/05/2017 15:31, Sebastian Huber wrote:
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testsuites/sptests/Makefile.am | 1 +
testsuites/sptests/configure.ac| 1 +
testsuites/sptests/spversion01/Makefile.am | 19 +
testsuites/sptests/spversion01/init.c | 55 +++