---
c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am | 5 +
.../arm/xilinx-zynq/include/zynq-slcr-regs.h | 111 +++++++++++++++++++++
.../lib/libbsp/arm/xilinx-zynq/include/zynq-slcr.h | 91 +++++++++++++++++
c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am | 8 ++
c/src/lib/libbsp/arm/xilinx-zynq/slcr/zynq-slcr.c | 101 +++++++++++++++++++
5 files changed, 316 insertions(+)
create mode 100644 c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr-regs.h
create mode 100644 c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr.h
create mode 100644 c/src/lib/libbsp/arm/xilinx-zynq/slcr/zynq-slcr.c
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
index 1f9ed59..08024b9 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am
@@ -49,6 +49,8 @@ include_bsp_HEADERS += include/i2c.h
include_bsp_HEADERS += include/irq.h
include_bsp_HEADERS += include/zynq-uart.h
include_bsp_HEADERS += include/zynq-uart-regs.h
+include_bsp_HEADERS += include/zynq-slcr.h
+include_bsp_HEADERS += include/zynq-slcr-regs.h
include_libcpu_HEADERS = ../../../libcpu/arm/shared/include/arm-cp15.h
@@ -118,6 +120,9 @@ libbsp_a_SOURCES += ../shared/arm-a9mpcore-clock-config.c
# I2C
libbsp_a_SOURCES += i2c/cadence-i2c.c
+# System Level Control Registers
+libbsp_a_SOURCES += slcr/zynq-slcr.c
+
# Cache
libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr-regs.h
b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr-regs.h
new file mode 100644
index 0000000..9759fd0
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr-regs.h
@@ -0,0 +1,111 @@
+/**
+ * @file
+ * @ingroup zynq_slcr
+ * @brief SLCR register definitions.
+ */
+
+/*
+ * Copyright (c) 2017
+ * NSF Center for High-Performance Reconfigurable Computing (CHREC),
+ * University of Pittsburgh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation
+ * are those of the authors and should not be interpreted as representing
+ * official policies, either expressed or implied, of CHREC.
+ *
+ * Author: Patrick Gauvin <gau...@hcs.ufl.edu>
+ */
+
+/**
+ * @defgroup zynq_slcr_regs SLCR Register Definitions
+ * @ingroup zynq_slcr
+ * @brief SLCR Register Definitions
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define ZYNQ_SLCR_BASE_ADDR ( 0xF8000000 )
+
+#define ZYNQ_SLCR_LOCK_OFF ( 0x4 )
+#define ZYNQ_SLCR_UNLOCK_OFF ( 0x8 )
+#define ZYNQ_SLCR_FPGA_RST_CTRL_OFF ( 0x240 )
+#define ZYNQ_SLCR_PSS_IDCODE_OFF ( 0x530 )
+#define ZYNQ_SLCR_LVL_SHFTR_EN_OFF ( 0x900 )
+
+#define ZYNQ_SLCR_LOCK_KEY ( 0x767b )
+#define ZYNQ_SLCR_UNLOCK_KEY ( 0xdf0d )
+
+/** \brief Get FPGA0_OUT_RST (bit 0) through FPGA3_OUT_RST fields (bit 3). */
+#define ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST_GET( reg ) \
+ BSP_FLD32GET( reg, 0, 3 )
+#define ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST( val ) BSP_FLD32( val, 0, 3 )
+
+/* NOTE: QEMU gives a value of 0 for the pss_idcode. */
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_GET( reg ) BSP_FLD32GET( reg, 12, 16 )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z007s ( 0x03 )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z012s ( 0x1c )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z014s ( 0x08 )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z010 ( 0x02 )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z015 ( 0x1b )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z020 ( 0x07 )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z030 ( 0x0c )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z035 ( 0x12 )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z045 ( 0x11 )
+#define ZYNQ_SLCR_PSS_IDCODE_DEVICE_7z100 ( 0x16 )
+
+#define ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE ( 0 )
+#define ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL ( 0xA )
+#define ZYNQ_SLCR_LVL_SHFTR_EN_ALL ( 0xF )
+
+static inline void zynq_slcr_write32(
+ const uint32_t reg_off,
+ const uint32_t val
+)
+{
+ volatile uint32_t *slcr_reg;
+ slcr_reg = (volatile uint32_t *)( ZYNQ_SLCR_BASE_ADDR + reg_off );
+ *slcr_reg = val;
+}
+
+static inline uint32_t zynq_slcr_read32(
+ const uint32_t reg_off
+)
+{
+ volatile uint32_t *slcr_reg;
+ slcr_reg = (volatile uint32_t *)( ZYNQ_SLCR_BASE_ADDR + reg_off);
+ return *slcr_reg;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_REGS_H */
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr.h
b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr.h
new file mode 100644
index 0000000..503cc15
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-slcr.h
@@ -0,0 +1,91 @@
+/**
+ * @file
+ * @ingroup zynq_slcr
+ * @brief SLCR support.
+ */
+
+/*
+ *
+ * Copyright (c) 2017
+ * NSF Center for High-Performance Reconfigurable Computing (CHREC),
+ * University of Pittsburgh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation
+ * are those of the authors and should not be interpreted as representing
+ * official policies, either expressed or implied, of CHREC.
+ *
+ * Author: Patrick Gauvin <gau...@hcs.ufl.edu>
+ */
+
+/**
+ * @defgroup zynq_slcr SLCR Support
+ * @ingroup arm_zynq
+ * @brief SLCR Support
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
+#define LIBBSP_ARM_XILINX_ZYNQ_SLCR_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Set the mask that allows the FPGA resets to be modified.
+ *
+ * Bit 0 corresponds to FPGA0_OUT_RST, and bit 3 to FPGA3_OUT_RST. Setting a
+ * bit in the mask to 1 allows calls to zynq_slcr_fpga_clk_rst to modify that
+ * reset. The default mask is 0xf.
+ */
+void zynq_slcr_fpga_clk_rst_mask_set(
+ uint32_t mask
+);
+
+/**
+ * @brief Control the FPGA reset values.
+ *
+ * @param val Bits 0 through 3 correspond to FPGA RST 0 through 3. A bit value
+ * of 1 asserts the reset.
+ */
+void zynq_slcr_fpga_clk_rst(
+ uint32_t val
+);
+
+/**
+ * @brief Control the level shifters between the PS and PL.
+ *
+ * @param val Acceptable values are ZYNQ_SLCR_LVL_SHFTR_EN_DISABLE,
+ * ZYNQ_SLCR_LVL_SHFTR_EN_PS_TO_PL, and ZYNQ_SLCR_LVL_SHFTR_EN_ALL.
+ */
+void zynq_slcr_level_shifter_enable(
+ uint32_t val
+);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_SLCR_H */
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
index a75c344..814095f 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am
@@ -150,6 +150,14 @@ $(PROJECT_INCLUDE)/bsp/zynq-uart-regs.h:
include/zynq-uart-regs.h $(PROJECT_INCL
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/zynq-uart-regs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/zynq-uart-regs.h
+$(PROJECT_INCLUDE)/bsp/zynq-slcr.h: include/zynq-slcr.h
$(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/zynq-slcr.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/zynq-slcr.h
+
+$(PROJECT_INCLUDE)/bsp/zynq-slcr-regs.h: include/zynq-slcr-regs.h
$(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/zynq-slcr-regs.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/zynq-slcr-regs.h
+
$(PROJECT_INCLUDE)/libcpu/arm-cp15.h:
../../../libcpu/arm/shared/include/arm-cp15.h
$(PROJECT_INCLUDE)/libcpu/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/arm-cp15.h
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/slcr/zynq-slcr.c
b/c/src/lib/libbsp/arm/xilinx-zynq/slcr/zynq-slcr.c
new file mode 100644
index 0000000..5492e2c
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/slcr/zynq-slcr.c
@@ -0,0 +1,101 @@
+/*
+ * SLCR Support Implementation
+ *
+ * At this point, only a few operations related to programming the FPGA are
+ * supported.
+ *
+ * Copyright (c) 2017
+ * NSF Center for High-Performance Reconfigurable Computing (CHREC),
+ * University of Pittsburgh. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+ * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+ * OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * The views and conclusions contained in the software and documentation
+ * are those of the authors and should not be interpreted as representing
+ * official policies, either expressed or implied, of CHREC.
+ *
+ * Author: Patrick Gauvin <gau...@hcs.ufl.edu>
+ */
+#include <stdint.h>
+#include <rtems.h>
+#include <bsp/zynq-slcr.h>
+#include <bsp/zynq-slcr-regs.h>
+
+static uint32_t rst_mask = 0xf;
+static rtems_interrupt_lock zynq_slcr_lock =
+ RTEMS_INTERRUPT_LOCK_INITIALIZER( "zynq_slcr" );
+
+static inline void slcr_unlock( void )
+{
+ zynq_slcr_write32( ZYNQ_SLCR_UNLOCK_OFF, ZYNQ_SLCR_UNLOCK_KEY );
+}
+
+static inline void slcr_lock( void )
+{
+ zynq_slcr_write32( ZYNQ_SLCR_LOCK_OFF, ZYNQ_SLCR_LOCK_KEY );
+}
+
+void zynq_slcr_fpga_clk_rst_mask_set(
+ uint32_t mask
+)
+{
+ rtems_interrupt_lock_context lcontext;
+
+ rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
+ rst_mask = 0xf & mask;
+ rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
+}
+
+void zynq_slcr_fpga_clk_rst(
+ uint32_t val
+)
+{
+ uint32_t rst_ctrl;
+ rtems_interrupt_lock_context lcontext;
+
+ rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
+ slcr_unlock();
+ rst_ctrl = ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST_GET(
+ zynq_slcr_read32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF )
+ );
+ /* Only modify resets that are set in the mask */
+ zynq_slcr_write32( ZYNQ_SLCR_FPGA_RST_CTRL_OFF,
+ ZYNQ_SLCR_FPGA_RST_CTRL_FPGA_OUT_RST(
+ ( ~rst_mask & rst_ctrl ) | ( rst_mask & val )
+ )
+ );
+ slcr_lock();
+ rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
+}
+
+void zynq_slcr_level_shifter_enable(
+ uint32_t val
+)
+{
+ rtems_interrupt_lock_context lcontext;
+
+ rtems_interrupt_lock_acquire( &zynq_slcr_lock, &lcontext );
+ slcr_unlock();
+ zynq_slcr_write32( ZYNQ_SLCR_LVL_SHFTR_EN_OFF, val );
+ slcr_lock();
+ rtems_interrupt_lock_release( &zynq_slcr_lock, &lcontext );
+}
--
2.7.4
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