Re: RISC-V interrupts in HiFive1

2017-08-16 Thread Denis Obrezkov
2017-08-16 10:27 GMT+02:00 Denis Obrezkov : > 2017-08-16 3:09 GMT+02:00 Hesham Almatary : > >> On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: >> > >> > >> > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov < >> denisobrez...@gmail.com> >> > wrote: >> >> >> >> 2017-08-16 2:06 GMT+02:00 Hesh

Re: RISC-V interrupts in HiFive1

2017-08-16 Thread Denis Obrezkov
2017-08-16 3:09 GMT+02:00 Hesham Almatary : > On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: > > > > > > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov > > > wrote: > >> > >> 2017-08-16 2:06 GMT+02:00 Hesham Almatary : > >>> > >>> / > >>> > >>> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obr

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Hesham Almatary
On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: > > > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov > wrote: >> >> 2017-08-16 2:06 GMT+02:00 Hesham Almatary : >>> >>> / >>> >>> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov >>> wrote: >>> > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >>

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Joel Sherrill
On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov wrote: > 2017-08-16 2:06 GMT+02:00 Hesham Almatary : > >> / >> >> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov >> wrote: >> > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >> >> >> >> >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >> wrote:

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-16 2:06 GMT+02:00 Hesham Almatary : > / > > On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov > wrote: > > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> > >> > >> > >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" > wrote: > >> > >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > >>> > >>> Hi

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Hesham Almatary
/ On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov wrote: > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: >> >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >>> >>> Hi Denis, >>> >>> You just need to modify riscv_interrupt_disable(). Read t

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 22:46 GMT+02:00 Denis Obrezkov : > 2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : >> >>> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >>> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: 2017-08-15 5:44 GMT+02:00

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >>> >>> >>> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >>> wrote: >>> >>> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >>> Hi Denis, You just n

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >> wrote: >> >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >> >>> Hi Denis, >>> >>> You just need to modify riscv_interrupt_disable(). Read the priv-spec

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 14:57 GMT+02:00 Joel Sherrill : > > > On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: > > 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > >> Hi Denis, >> >> You just need to modify riscv_interrupt_disable(). Read the priv-spec >> manual for your RISC-V version, and determine which bit s

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Joel Sherrill
On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > Hi Denis, > > You just need to modify riscv_interrupt_disable(). Read the priv-spec > manual for your RISC-V version, and determine which bit should be > cleared (it's called MIE in priv-1.10, but you

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 5:44 GMT+02:00 Hesham Almatary : > Hi Denis, > > You just need to modify riscv_interrupt_disable(). Read the priv-spec > manual for your RISC-V version, and determine which bit should be > cleared (it's called MIE in priv-1.10, but you mentioned you work with > priv-1.9). > > Cheers, >

Re: RISC-V interrupts in HiFive1

2017-08-14 Thread Hesham Almatary
Hi Denis, You just need to modify riscv_interrupt_disable(). Read the priv-spec manual for your RISC-V version, and determine which bit should be cleared (it's called MIE in priv-1.10, but you mentioned you work with priv-1.9). Cheers, Hesham On Mon, Aug 14, 2017 at 6:10 PM, Denis Obrezkov wrot