2017-08-15 5:44 GMT+02:00 Hesham Almatary <heshamelmat...@gmail.com>:
> Hi Denis, > > You just need to modify riscv_interrupt_disable(). Read the priv-spec > manual for your RISC-V version, and determine which bit should be > cleared (it's called MIE in priv-1.10, but you mentioned you work with > priv-1.9). > > Cheers, > Hesham > > On Mon, Aug 14, 2017 at 6:10 PM, Denis Obrezkov <denisobrez...@gmail.com> > wrote: > > Hello all, > > > > at the end of the GSoC I've found out that interrupts in my BSP > > weren't properly enabled/disabled globally. > > This happens because my work is based on the Hesham's > > BSP for RISC-V and it was done for the previous version of ISA. > > Thus, the Hesham's interrupt enabling/disabling instructions did > > nothing in my version of ISA. > > I've tried to fix this issue, but without much of success. > > > > -- > > Regards, Denis Obrezkov > > > > _______________________________________________ > > devel mailing list > > devel@rtems.org > > http://lists.rtems.org/mailman/listinfo/devel > > > > -- > Hesham > Yes, I've already done it, but it doesn't work. It just staying disabled after some amount of ticks. -- Regards, Denis Obrezkov
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