Re: RISC-V interrupts in HiFive1

2017-08-16 Thread Denis Obrezkov
2017-08-16 10:27 GMT+02:00 Denis Obrezkov : > 2017-08-16 3:09 GMT+02:00 Hesham Almatary : > >> On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: >> > >> > >> > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov < >> denisobrez...@gmail.com> >> > wrote: >> >> >> >> 2017-08-16 2:06 GMT+02:00 Hesh

Re: RISC-V interrupts in HiFive1

2017-08-16 Thread Denis Obrezkov
2017-08-16 3:09 GMT+02:00 Hesham Almatary : > On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: > > > > > > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov > > > wrote: > >> > >> 2017-08-16 2:06 GMT+02:00 Hesham Almatary : > >>> > >>> / > >>> > >>> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obr

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Hesham Almatary
On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: > > > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov > wrote: >> >> 2017-08-16 2:06 GMT+02:00 Hesham Almatary : >>> >>> / >>> >>> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov >>> wrote: >>> > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >>

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Joel Sherrill
On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov wrote: > 2017-08-16 2:06 GMT+02:00 Hesham Almatary : > >> / >> >> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov >> wrote: >> > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >> >> >> >> >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >> wrote:

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-16 2:06 GMT+02:00 Hesham Almatary : > / > > On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov > wrote: > > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> > >> > >> > >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" > wrote: > >> > >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > >>> > >>> Hi

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Hesham Almatary
/ On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov wrote: > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: >> >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >>> >>> Hi Denis, >>> >>> You just need to modify riscv_interrupt_disable(). Read t

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 22:46 GMT+02:00 Denis Obrezkov : > 2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : >> >>> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >>> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: 2017-08-15 5:44 GMT+02:00

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >>> >>> >>> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >>> wrote: >>> >>> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >>> Hi Denis, You just n

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >> wrote: >> >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >> >>> Hi Denis, >>> >>> You just need to modify riscv_interrupt_disable(). Read the priv-spec

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 14:57 GMT+02:00 Joel Sherrill : > > > On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: > > 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > >> Hi Denis, >> >> You just need to modify riscv_interrupt_disable(). Read the priv-spec >> manual for your RISC-V version, and determine which bit s

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Joel Sherrill
On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > Hi Denis, > > You just need to modify riscv_interrupt_disable(). Read the priv-spec > manual for your RISC-V version, and determine which bit should be > cleared (it's called MIE in priv-1.10, but you

Re: RISC-V interrupts in HiFive1

2017-08-15 Thread Denis Obrezkov
2017-08-15 5:44 GMT+02:00 Hesham Almatary : > Hi Denis, > > You just need to modify riscv_interrupt_disable(). Read the priv-spec > manual for your RISC-V version, and determine which bit should be > cleared (it's called MIE in priv-1.10, but you mentioned you work with > priv-1.9). > > Cheers, >

Re: RISC-V interrupts in HiFive1

2017-08-14 Thread Hesham Almatary
Hi Denis, You just need to modify riscv_interrupt_disable(). Read the priv-spec manual for your RISC-V version, and determine which bit should be cleared (it's called MIE in priv-1.10, but you mentioned you work with priv-1.9). Cheers, Hesham On Mon, Aug 14, 2017 at 6:10 PM, Denis Obrezkov wrot

Re: RISC-V interrupts

2017-06-11 Thread Hesham Almatary
On Mon, Jun 12, 2017 at 6:11 AM, Denis Obrezkov wrote: > 2017-06-11 22:38 GMT+03:00 Hesham Almatary : >> >> Hi Denis, >> >> As per my previous reply, it is gonna be a challenge to make RTEMS >> exes fit in 16 KiB of RAM, so it's a good idea to do some analysis on >> the compressed ISA. >> >> Cheer

Re: RISC-V interrupts

2017-06-11 Thread Denis Obrezkov
2017-06-11 22:38 GMT+03:00 Hesham Almatary : > Hi Denis, > > As per my previous reply, it is gonna be a challenge to make RTEMS > exes fit in 16 KiB of RAM, so it's a good idea to do some analysis on > the compressed ISA. > > Cheers, > Hesham > > Ok, I will investigate this. Also, there is 8 KiB o

Re: RISC-V interrupts

2017-06-11 Thread Hesham Almatary
Hi Denis, As per my previous reply, it is gonna be a challenge to make RTEMS exes fit in 16 KiB of RAM, so it's a good idea to do some analysis on the compressed ISA. Cheers, Hesham On Sun, Jun 11, 2017 at 9:36 PM, Denis Obrezkov wrote: > I found out that there is 16 KiB of RAM. So, Freedom E31

Re: RISC-V interrupts

2017-06-11 Thread Denis Obrezkov
I found out that there is 16 KiB of RAM. So, Freedom E310 chip has only 16 KiB of RAM. And Freedeom E310 chip is based on E31 Coreplex core that allows maximum of 64 KiB of RAM. So, I was just a bit confused with these names at first. 2017-06-09 11:49 GMT+03:00 Hesham Almatary : > On Fri, Jun 9,

Re: RISC-V interrupts

2017-06-09 Thread Hesham Almatary
On Fri, Jun 9, 2017 at 9:09 AM, Denis Obrezkov wrote: > 2017-06-09 1:52 GMT+03:00 Hesham Almatary : >> >> Hi Denis, >> >> Does your board support any accesses to > 0x8000. Note you still >> use such region in your linker script, which shouldn't be used if your >> board doesn't support it. I'd

Re: RISC-V interrupts

2017-06-08 Thread Chris Johns
On 09/06/2017 09:09, Denis Obrezkov wrote: > > I think I found the problem. It seems that this gdb build supports 16 KiB of > RAM > (as in Freedom E300 specification). > I changed the value of RAM length to 16 KiB, so now I can execute further. > Thanks! > Some gdb simulators have target optio

Re: RISC-V interrupts

2017-06-08 Thread Denis Obrezkov
2017-06-09 1:52 GMT+03:00 Hesham Almatary : > Hi Denis, > > Does your board support any accesses to > 0x8000. Note you still > use such region in your linker script, which shouldn't be used if your > board doesn't support it. I'd suggest your read about memory mapping > on your board and fix t

Re: RISC-V interrupts

2017-06-08 Thread Hesham Almatary
Hi Denis, Does your board support any accesses to > 0x8000. Note you still use such region in your linker script, which shouldn't be used if your board doesn't support it. I'd suggest your read about memory mapping on your board and fix the linker script accordingly. Regards, Hesham On Fri,

Re: RISC-V interrupts

2017-06-08 Thread Denis Obrezkov
2017-06-08 17:49 GMT+03:00 Denis Obrezkov : > 2017-06-08 12:24 GMT+03:00 Denis Obrezkov : > >> 2017-06-07 22:41 GMT+03:00 Hesham Almatary : >> >>> On Thu, Jun 8, 2017 at 2:26 AM, Denis Obrezkov >>> wrote: >>> > 2017-06-07 14:44 GMT+03:00 Sebastian Huber >>> > : >>> >> >>> >> On 06/06/17 18:58, He

Re: RISC-V interrupts

2017-06-08 Thread Denis Obrezkov
2017-06-08 12:24 GMT+03:00 Denis Obrezkov : > 2017-06-07 22:41 GMT+03:00 Hesham Almatary : > >> On Thu, Jun 8, 2017 at 2:26 AM, Denis Obrezkov >> wrote: >> > 2017-06-07 14:44 GMT+03:00 Sebastian Huber >> > : >> >> >> >> On 06/06/17 18:58, Hesham Almatary wrote: >> >> >> >>> Originally RTEMS had a

Re: RISC-V interrupts

2017-06-08 Thread Denis Obrezkov
2017-06-07 22:41 GMT+03:00 Hesham Almatary : > On Thu, Jun 8, 2017 at 2:26 AM, Denis Obrezkov > wrote: > > 2017-06-07 14:44 GMT+03:00 Sebastian Huber > > : > >> > >> On 06/06/17 18:58, Hesham Almatary wrote: > >> > >>> Originally RTEMS had a one big linkcmd for each platform, which > >>> defines

Re: RISC-V interrupts

2017-06-07 Thread Hesham Almatary
On Thu, Jun 8, 2017 at 2:26 AM, Denis Obrezkov wrote: > 2017-06-07 14:44 GMT+03:00 Sebastian Huber > : >> >> On 06/06/17 18:58, Hesham Almatary wrote: >> >>> Originally RTEMS had a one big linkcmd for each platform, which >>> defines linker symbols (used in C code) and required sections. This >>>

Re: RISC-V interrupts

2017-06-07 Thread Gedare Bloom
On Wed, Jun 7, 2017 at 12:26 PM, Denis Obrezkov wrote: > 2017-06-07 14:44 GMT+03:00 Sebastian Huber > : >> >> On 06/06/17 18:58, Hesham Almatary wrote: >> >>> Originally RTEMS had a one big linkcmd for each platform, which >>> defines linker symbols (used in C code) and required sections. This >>>

Re: RISC-V interrupts

2017-06-07 Thread Denis Obrezkov
2017-06-07 14:44 GMT+03:00 Sebastian Huber : > On 06/06/17 18:58, Hesham Almatary wrote: > > Originally RTEMS had a one big linkcmd for each platform, which >> defines linker symbols (used in C code) and required sections. This >> has been improved with current BSPs (like ARM-based ones), by >> sp

Re: RISC-V interrupts

2017-06-07 Thread Sebastian Huber
On 06/06/17 18:58, Hesham Almatary wrote: Originally RTEMS had a one big linkcmd for each platform, which defines linker symbols (used in C code) and required sections. This has been improved with current BSPs (like ARM-based ones), by splitting up shared linkcmd parts (linkcmd base) and BSP spe

Re: RISC-V interrupts

2017-06-06 Thread Hesham Almatary
Hi Denis, In riscv_generic, only context switching is supported. It was supposed to only run hello world (console) and ticker (tickless timer), both don't need interrupts. I assume you can do the same for HiFive1, which is the simplest. Then we can discuss about the timer and interrupt implementat