Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Sachin Ghadi
On Wed, Jun 5, 2019 at 4:36 PM Sebastian Huber wrote: > > On 05/06/2019 12:20, Sachin Ghadi wrote: > > Thanks Sebastian, > > > > On Wed, Jun 5, 2019 at 10:41 AM Sebastian Huber > > wrote: > >> Hello Sachin, > >> > >> On 05/06/2019 06:15, sachin.gh...@sifive.com wrote: > >>> Hi RTEMS dev team, > >

Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Hesham Almatary
On Wed, 5 Jun 2019 at 15:14, Sebastian Huber wrote: > > On 05/06/2019 15:09, Hesham Almatary wrote: > > On Wed, 5 Jun 2019 at 07:11, Sebastian Huber > > wrote: > >> Hello Sachin, > >> > >> On 05/06/2019 06:15,sachin.gh...@sifive.com wrote: > >>> Hi RTEMS dev team, > >>> > >>> I don’t know if I

Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Sebastian Huber
On 05/06/2019 15:09, Hesham Almatary wrote: Upstream QEMU runs RTEMS fine with -virt board. Also, I tested 32-bit RTEMS variants on Zynq-based FPGA with Bluespec cores, UART and DTB [1]. [1]https://github.com/bluespec/Piccolo It would be great if you could mention this on the BSP page somehow:

Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Sebastian Huber
On 05/06/2019 15:09, Hesham Almatary wrote: On Wed, 5 Jun 2019 at 07:11, Sebastian Huber wrote: Hello Sachin, On 05/06/2019 06:15,sachin.gh...@sifive.com wrote: Hi RTEMS dev team, I don’t know if I should send this query to users list or developer list. I am working on the getting RTEMS B

Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Hesham Almatary
On Wed, 5 Jun 2019 at 07:11, Sebastian Huber wrote: > > Hello Sachin, > > On 05/06/2019 06:15, sachin.gh...@sifive.com wrote: > > > > Hi RTEMS dev team, > > > > I don’t know if I should send this query to users list or developer list. > > > > I am working on the getting RTEMS BSP ported on the one

Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Joel Sherrill
On Tue, Jun 4, 2019, 11:15 PM wrote: > Hi RTEMS dev team, > > I don’t know if I should send this query to users list or developer list. > > I am working on the getting RTEMS BSP ported on the one of RISC-V based > SoC. > > Current RTEMS has support only for Spike simulator. > > > > It looks like

Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Sebastian Huber
On 05/06/2019 12:20, Sachin Ghadi wrote: Thanks Sebastian, On Wed, Jun 5, 2019 at 10:41 AM Sebastian Huber wrote: Hello Sachin, On 05/06/2019 06:15, sachin.gh...@sifive.com wrote: Hi RTEMS dev team, I don’t know if I should send this query to users list or developer list. I am working on t

Re: RTEMS on embedded CPUs(RISCV)

2019-06-05 Thread Sachin Ghadi
Thanks Sebastian, On Wed, Jun 5, 2019 at 10:41 AM Sebastian Huber wrote: > > Hello Sachin, > > On 05/06/2019 06:15, sachin.gh...@sifive.com wrote: > > > > Hi RTEMS dev team, > > > > I don’t know if I should send this query to users list or developer list. > > > > I am working on the getting RTEMS

Re: RTEMS on embedded CPUs(RISCV)

2019-06-04 Thread Sebastian Huber
Hello Sachin, On 05/06/2019 06:15, sachin.gh...@sifive.com wrote: Hi RTEMS dev team, I don’t know if I should send this query to users list or developer list. I am working on the getting RTEMS BSP ported on the one of RISC-V based SoC. Current RTEMS has support only for Spike simulator.

RTEMS on embedded CPUs(RISCV)

2019-06-04 Thread sachin.ghadi
Hi RTEMS dev team, I don't know if I should send this query to users list or developer list. I am working on the getting RTEMS BSP ported on the one of RISC-V based SoC. Current RTEMS has support only for Spike simulator. It looks like RTEMS does not fit very well on the systems having less