On 2014-07-07 09:46, Daniel Cederman wrote:
Probably true. I could change
rtems_cache_invalidate_entire_instruction_cpu_set(set) to
rtems_cache_invalidate_entire_instruction_all_processors() instead. Or make the
original rtems_cache_invalidate_entire_instruction() notify all processors when
runni
Probably true. I could change
rtems_cache_invalidate_entire_instruction_cpu_set(set) to
rtems_cache_invalidate_entire_instruction_all_processors() instead. Or
make the original rtems_cache_invalidate_entire_instruction() notify all
processors when running SMP, but I guess that could be dangerou
I think instruction cache operations scoped by processors make no sense on SMP.
Every processor should have the same view to the instruction memory.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41-16
Fax : +49 89 189 47
On 2014-07-04 17:12, Daniel Cederman wrote:
> This limits the API to the default cpu_set_t. Other routines like
> pthread_setaffinity_np() don't have this limitation.
I looked at pthread_setaffinity_np() and got a bit confused. I see that it
takes both a pointer to a cpu_set_t and the size of
On Jul 4, 2014 10:09 AM, Daniel Cederman wrote:
>
> > This limits the API to the default cpu_set_t. Other routines like
> > pthread_setaffinity_np() don't have this limitation.
>
> I looked at pthread_setaffinity_np() and got a bit confused. I see that
> it takes both a pointer to a cpu_set_t a
> This limits the API to the default cpu_set_t. Other routines like
> pthread_setaffinity_np() don't have this limitation.
I looked at pthread_setaffinity_np() and got a bit confused. I see that
it takes both a pointer to a cpu_set_t and the size of the cpu set. It
forwards it to _Scheduler_Se
On 2014-07-04 11:56, Daniel Cederman wrote:
> With this implementation cache routines must not be called from
> interrupt context. This should be mentioned in the documentation.
>
> It is extremely difficult to implement it in a way so that it can be
> used from interrupt context.
There a
Thank you for you comments Sebastian!
> With this implementation cache routines must not be called from
> interrupt context. This should be mentioned in the documentation.
>
> It is extremely difficult to implement it in a way so that it can be
> used from interrupt context.
There are some sync
On 2014-07-03 11:37, Daniel Cederman wrote:
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. Implementatio
Comments inline. But mostly the same style comments.
Check that they aren't needed in other places. I didn't
note them everywhere.
On 7/3/2014 4:37 AM, Daniel Cederman wrote:
> Adds functions that allows the user to specify which cores that should
> perform the cache operation. SMP messages are se
Adds functions that allows the user to specify which cores that should
perform the cache operation. SMP messages are sent to all the specified
cores and the caller waits until all cores have acknowledged that they
have flushed their cache. Implementation is shown using both function
pointers and fu
11 matches
Mail list logo
