On 2014-07-09 16:38, Gedare Bloom wrote:
On Wed, Jul 9, 2014 at 3:02 AM, Daniel Cederman wrote:
Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not
On Wed, Jul 9, 2014 at 3:02 AM, Daniel Cederman wrote:
> Changes to the trap table might be missed by other cores.
> If the system state is up, the other cores can be notified
> using SMP messages that they need to flush their icache.
> If the up state has not been reached there is no need to
> no
Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache ju
