Changes to the trap table might be missed by other cores.
If the system state is up, the other cores can be notified
using SMP messages that they need to flush their icache.
If the up state has not been reached there is no need to
notify other cores. They will do an automatic flush of the
icache just after entering the up state, but before enabling
interrupts.
---
cpukit/score/cpu/sparc/cpu.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c
index c616de4..88228b7 100644
--- a/cpukit/score/cpu/sparc/cpu.c
+++ b/cpukit/score/cpu/sparc/cpu.c
@@ -210,10 +210,16 @@ void _CPU_ISR_install_raw_handler(
(u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
- /* need to flush icache after this !!! */
-
+ /*
+ * Changes to the trap table might be missed by other cores.
+ * If the system state is up, the other cores can be notified
+ * using SMP messages that they need to flush their icache.
+ * If the up state has not been reached there is no need to
+ * notify other cores. They will do an automatic flush of the
+ * icache just after entering the up state, but before enabling
+ * interrupts.
+ */
rtems_cache_invalidate_entire_instruction();
-
}
void _CPU_ISR_install_vector(
--
1.7.9.5
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