On 4/13/21 7:44 AM, Sebastian Huber wrote:
On 12/04/2021 21:40, Jiri Gaisler wrote:
I just realized that I can change the patch from an assembly WFI to a simple busy loop instead. This would work on any architecture without assembly. Should I provide a new patch with this cleaner solution?
On 12/04/2021 21:40, Jiri Gaisler wrote:
I just realized that I can change the patch from an assembly WFI to a
simple busy loop instead. This would work on any architecture without
assembly. Should I provide a new patch with this cleaner solution?
You can use
(void) _CPU_Thread_Idle_body(
On Mon, Apr 12, 2021 at 1:40 PM Jiri Gaisler wrote:
>
>
> On 4/12/21 8:44 PM, Gedare Bloom wrote:
> > Hi Jiri,
> >
> > How much do you think this is a RISC-V specific problem, or one that
> > may affect other SMP processors? Should we add an RTEMS API for this
> > capability instead of shimming so
On 4/12/21 8:44 PM, Gedare Bloom wrote:
Hi Jiri,
How much do you think this is a RISC-V specific problem, or one that
may affect other SMP processors? Should we add an RTEMS API for this
capability instead of shimming some Asm into a test case?
It's bound to happen on any architecture/loader
Hi Jiri,
How much do you think this is a RISC-V specific problem, or one that
may affect other SMP processors? Should we add an RTEMS API for this
capability instead of shimming some Asm into a test case?
On Sun, Apr 11, 2021 at 1:30 PM Jiri Gaisler wrote:
>
> smpfatal08 fails on SMP RISC-V syst
722f8363fe131801ebb9f733f836d0bf6cd82c7a Mon Sep 17 00:00:00 2001
From: Jiri Gaisler
Date: Sun, 11 Apr 2021 21:15:13 +0200
Subject: [PATCH] smpfatal08: halt secondary RISC-V processors
* On most RISC-V platforms, all cpus are started by the
boot-loader. We need to stop the secondary cpus or they
will clobber the test
