On 26/06/2019 09:07, Chris Johns wrote:
#if defined(__ARM_ARCH_7A__)
if (MPIDR & (1 << 39) == 0) {
if ((MPIDR & (1 << 30)) == 0) {
arm_cp15_tlb_invalidate_entry_all_asids(mva);
}
else
#endif
{
arm_cp15_tlb_instruction_invalidate_entry(mva);
arm_cp15_tlb_data_inval
On 26/6/19 3:53 pm, Sebastian Huber wrote:
> On 26/06/2019 00:22, Chris Johns wrote:
>> On 25/6/19 9:59 pm, Sebastian Huber wrote:
>>> Can't you use the
>>>
>>> B4.1.94 ID_PFR1, Processor Feature Register 1, VMSA
>>>
>>> and test for the Virtualization Extensions?
>>
>> This is a neater solution. C
On 26/06/2019 00:22, Chris Johns wrote:
On 25/6/19 9:59 pm, Sebastian Huber wrote:
Can't you use the
B4.1.94 ID_PFR1, Processor Feature Register 1, VMSA
and test for the Virtualization Extensions?
This is a neater solution. Can I assume the ASID support part of the
virtualization extensions
On 25/6/19 9:59 pm, Sebastian Huber wrote:
> Can't you use the
>
> B4.1.94 ID_PFR1, Processor Feature Register 1, VMSA
>
> and test for the Virtualization Extensions?
This is a neater solution. Can I assume the ASID support part of the
virtualization extensions and op 3 is consistent?
>
> I am
Can't you use the
B4.1.94 ID_PFR1, Processor Feature Register 1, VMSA
and test for the Virtualization Extensions?
I am not sure if pre ARMv7-AR processors have this register.
--
Sebastian Huber, embedded brains GmbH
Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone : +49 89 189 47 41
From: Chris Johns
Closes #3760
---
bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
b/bsps/arm/shared/cp15/arm-cp15-set-ttb-entries.c
index c2be0f566e..8e261366ed
