out! ERROR:../hw/riscv/boot.c:164:riscv_load_firmware: \
assertion failed: (firmware_filename != NULL)
Use an approach similar to riscv_find_and_load_firmware().
Reported-by: Daniel Henrique Barboza
Signed-off-by: Sebastian Huber
---
hw/riscv/microchip_pfsoc.c | 12 +++-
1 file
Hello Joel,
I update it through a script, however, after an update usually something is
broken and you have to write a bug report or a patch. I was busy with other
things recently.
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e
comments in line with these
guidelines were replaced by incomplete comments not following the guidelines.
From an RTEMS Project point of view, are these guidelines still relevant?
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email: sebastia
- Am 4. Jul 2024 um 20:18 schrieb o...@c-mauderer.de:
> Hello Joel and Sebastian,
>
> Am 04.07.24 um 19:38 schrieb Sebastian Huber:
>> - Am 4. Jul 2024 um 19:30 schrieb Joel Sherrill j...@rtems.org:
>>
>>> Thanks. What times?
>>
>> About 7 min
- Am 4. Jul 2024 um 19:30 schrieb Joel Sherrill j...@rtems.org:
> Thanks. What times?
About 7 minutes past 4, 12, and 20 CEST.
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email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 7
- Am 4. Jul 2024 um 18:12 schrieb Joel Sherrill j...@rtems.org:
> On Thu, Jul 4, 2024, 1:06 AM Sebastian Huber <
> sebastian.hu...@embedded-brains.de> wrote:
>
>> - Am 3. Jul 2024 um 19:29 schrieb Joel Sherrill j...@rtems.org:
>>
>> > Hi
>> >
- Am 3. Jul 2024 um 19:29 schrieb Joel Sherrill j...@rtems.org:
> Hi
>
> When/how do the mirrors of gcc, binutlls, newlib, etc get updated?
They are updated once a day.
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email:
On 29.06.24 02:30, Gedare Bloom wrote:
On Fri, Jun 28, 2024 at 10:41 AM Gedare Bloom wrote:
On Thu, Jun 27, 2024 at 11:39 PM Sebastian Huber
wrote:
On 28.06.24 00:42, Gedare Bloom wrote:
I've been doing back through my third-party source code attribution.
I've found that there
f them?
These files are included from Newlib header files and are used by the
legacy network stack and libbsd.
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phone: +49-89-18 94 741 - 16
fax: +4
Hello John,
I have some issues on arm and Ada with current versions of GCC, see also:
https://gcc.gnu.org/pipermail/gcc/2024-June/244197.html
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email: sebastian.hu...@embedded-brains.de
phone: +49-89-1
On 14.06.24 11:47, Sebastian Huber wrote:
Hello,
an user noticed that for example on the Xilinx Zynq 7000 BSP, the
rtems_cache_disable_data() doesn't work.
I had a look at this and managed to disable the L1 and L2 caches,
however, afterwards I got not that far. On the Cortex-A cor
On 18.06.24 17:32, Gedare Bloom wrote:
On Mon, Jun 17, 2024 at 11:20 PM Chris Johns wrote:
On 18/6/2024 12:02 am, Sebastian Huber wrote:
On 17.06.24 03:35, Chris Johns wrote:
On 14/6/2024 10:42 pm, Peter Dufault wrote:
On Jun 14, 2024, at 5:47 AM, Sebastian Huber
wrote:
Hello,
an
On 17.06.24 03:35, Chris Johns wrote:
On 14/6/2024 10:42 pm, Peter Dufault wrote:
On Jun 14, 2024, at 5:47 AM, Sebastian Huber
wrote:
Hello,
an user noticed that for example on the Xilinx Zynq 7000 BSP, the
rtems_cache_disable_data() doesn't work.
I had a look at this and manag
_data() and let it
return RTEMS_UNSATISFIED for example.
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Registernu
show up in the right spot in the group hierarchy. Not really a lot of
people work on this task.
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phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
R
Hello Martin,
I suggest to remove the grlib/l2c cache support and make sure that
everything is available through the RTEMS Cache Manager.
On 16.01.24 16:48, Sebastian Huber wrote:
Hello Martin,
we have also the Cache Manager support in
bsps/sparc/leon3/start/cache.c. At least the lock
On 14.05.24 17:11, Kinsey Moore wrote:
On Tue, May 14, 2024 at 1:28 AM Chris Johns <mailto:chr...@rtems.org>> wrote:
On 14/5/2024 4:04 pm, Sebastian Huber wrote:
> Hello,
>
> the ZynqMP APU RAM start addresses are far away from 0x0:
>
> cat
ould it be possible to add
a NULL pointer protection page?
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On 08.05.24 08:17, Sebastian Huber wrote:
Hello,
on the arm target, we use this:
static inline struct Per_CPU_Control *_ARM_Get_current_per_CPU_control(
void )
{
struct Per_CPU_Control *cpu_self;
/* Use PL1 only Thread ID Register (TPIDRPRW) */
__asm__ volatile (
"mrc p
BSP-specific startup code has to decode the MPIDR and set the thread
ID register accordingly.
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Regi
Sorry, this did go to the wrong mailing list.
On 07.05.24 14:56, Sebastian Huber wrote:
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
Registers, GICD_ISPENDRn":
"In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
processor
According to the GICv2 specification section 4.3.7, "Interrupt Set-Pending
Registers, GICD_ISPENDRn":
"In a multiprocessor implementation, GICD_ISPENDR0 is banked for each connected
processor. This register holds the Set-pending bits for interrupts 0-31."
Signed-off-by: Seba
rupt makes that
interrupt pending on that CPU interface
- removing a CPU interface from the target list of a pending interrupt
removes the pending state of that interrupt on that CPU interface."
Signed-off-by: Sebastian Huber
---
hw/intc/arm_gic.c | 7 +++
1 file changed, 7 inserti
t declaration of function 'sinl'; did you mean 'sinf'?
[-Wimplicit-function-declaration]
43 | w = coshl(x) * cosl(y) + (sinhl(x) * sinl(y)) * I;
| ^~~~
| sinf
make[4
Hello,
in order to build the nios2 GCC 14, you have to add --enable-obsolete to
the configure command line. With this option, it builds fine. I am not
sure how this option can be added to the RSB just for this target.
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8
Keep RTEMS up to date with the upstream development.
---
rtems/config/tools/rtems-gcc-10-newlib-head.cfg | 4 ++--
rtems/config/tools/rtems-gcc-10.4-newlib-head.cfg | 4 ++--
rtems/config/tools/rtems-gcc-12-newlib-head.cfg | 4 ++--
rtems/config/tools/rtems-gcc-13-newlib-head.cfg | 4 ++--
r
Keep RTEMS up to date with the upstream development.
For GCC 13, this includes a new set of aarch64 multilibs to address Cortex-A53
workarounds and fixes for powerpc.
---
rtems/config/tools/rtems-gcc-12-newlib-head.cfg | 4 ++--
rtems/config/tools/rtems-gcc-13-newlib-head.cfg | 4 ++--
2 files ch
Keep RTEMS up to date with the upstream development. This snapshot is close to
the GCC 14 release.
---
rtems/config/tools/rtems-binutils-head.cfg| 4 ++--
rtems/config/tools/rtems-gcc-head-newlib-head.cfg | 4 ++--
rtems/config/tools/rtems-gdb-head.cfg | 4 ++--
3 files change
are checked in. How
will the ticket updates work in GitLab? Are the ticket numbers the same?
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741
Make the kernel I/O output character device processing configurable
through an option set parameter. Add RTEMS_IO_NO_OUTPUT and
RTEMS_IO_DRAIN options. The goal of this API change is to enable
draining the kernel output device in the system termination process
before a reset is issued. A use cas
On 16.04.24 07:25, Sebastian Huber wrote:
On 09.04.24 16:28, Sebastian Huber wrote:
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the
On 24.04.24 14:37, Cedric Berger wrote:
Hello Sebastian,
On 23.04.2024 19:56, Sebastian Huber wrote:
1. Are all the things need for the release resolved? Tickets reviewed?
It would be nice to have the interrupt get/set priority API in RTEMS 6. The
Cortex-M floating point issue is not yet
Update #4982.
---
bsps/arm/tms570/start/tms570_sys_core.S | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/bsps/arm/tms570/start/tms570_sys_core.S
b/bsps/arm/tms570/start/tms570_sys_core.S
index 83dee26ec8..ef28d88ede 100644
--- a/bsps/arm/tms570/start/tms570_sys_core.S
+++ b/b
The performance monitor counter is stopped when the core is waiting for
interrupts.
Update #4982.
---
bsps/arm/tms570/clock/clock.c | 71 --
bsps/arm/tms570/cpucounter/cpucounterread.c | 83 -
spec/build/bsps/arm/tms570/obj.yml | 1 -
3
Update #4982.
---
bsps/arm/tms570/clock/clock.c | 15 ---
bsps/include/bsp/fatal.h | 3 +++
2 files changed, 7 insertions(+), 11 deletions(-)
diff --git a/bsps/arm/tms570/clock/clock.c b/bsps/arm/tms570/clock/clock.c
index cf14d5772f..2fb884b3ce 100644
--- a/bsps/arm/tms570/cloc
Update #4982.
---
cpukit/score/cpu/arm/include/libcpu/arm-cp15.h | 17 +
1 file changed, 17 insertions(+)
diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h
index c239eaccc8..4a5ddb561e 100644
--- a/cpukit/score/cpu/arm/in
The clock tick rate was off by a factor of two in some configurations.
Use the maximum counter frequency to get the best time resolution. Do
not use the automatic interrupt clear feature.
Update #4982.
---
bsps/arm/tms570/clock/clock.c | 99 +++
1 file changed, 32
Update #4982.
---
bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h | 27 +++
1 file changed, 27 insertions(+)
diff --git a/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
b/bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h
index d5583a1cca..1ca2bff685 100644
--- a/bsps/arm/tms570/include/
Update #4982.
---
bsps/arm/tms570/clock/clock.c | 4 ++--
bsps/arm/tms570/console/tms570-sci.c| 2 +-
bsps/arm/tms570/cpucounter/cpucounterread.c | 2 +-
bsps/arm/tms570/include/bsp.h | 6 --
spec/build/bsps/arm/tms570/grp.yml | 12
The rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size() functions shall return the entire
cache size for a level of 0. Levels greater than 0 shall return the size of
the associated level.
Update #4982.
---
bsps/arm/shared/cache/cache-cp15.c | 8
1 file changed
Update #4982.
---
bsps/arm/shared/cache/cache-cp15.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/bsps/arm/shared/cache/cache-cp15.c
b/bsps/arm/shared/cache/cache-cp15.c
index 88fae2fb1f..92ccfcb276 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/ar
Sebastian Huber (9):
arm: Add arm_cp15_data_cache_all_invalidate()
bsps/cache: Simplify Cortex-R5 cache support
bsps/cache: Fix ARM CP-15 get cache size
bsp/tms570: Add TMS570LC4357 PLL support
bsp/tms570: Add clock BSP options
bsp/tms570: Fix clock driver
bsp/tms570: Add
---
bsps/arm/shared/cache/cache-cp15.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/bsps/arm/shared/cache/cache-cp15.c
b/bsps/arm/shared/cache/cache-cp15.c
index d78ec4feb4..88fae2fb1f 100644
--- a/bsps/arm/shared/cache/cache-cp15.c
+++ b/bsps/arm/shared/cache/cache-cp
*/
+
+/**
+ * @file
+ *
+ * @ingroup RTEMSDriverClockArmv7MSysTick
+ *
+ * @brief This header file provides support for Armv7-M clock drivers.
+ */
+
/*
- * Copyright (c) 2011, 2018 Sebastian Huber. All rights reserved.
+ * Copyright (C) 2024 embedded brains GmbH & Co. KG
+ * Copyright (C) 2011,
---
bsps/arm/shared/doxygen.h | 56 +++
1 file changed, 56 insertions(+)
diff --git a/bsps/arm/shared/doxygen.h b/bsps/arm/shared/doxygen.h
index 469928d712..8dbf129f07 100644
--- a/bsps/arm/shared/doxygen.h
+++ b/bsps/arm/shared/doxygen.h
@@ -29,3 +29,59 @@
Fix typos.
---
bsps/aarch64/include/bsp/linker-symbols.h | 2 +-
bsps/aarch64/include/bsp/start.h | 2 +-
bsps/aarch64/shared/doxygen.h | 23 +++
3 files changed, 25 insertions(+), 2 deletions(-)
create mode 100644 bsps/aarch64/shared/doxygen.h
diff --g
---
cpukit/score/cpu/aarch64/aarch64-thread-idle.c | 7 +--
cpukit/score/cpu/aarch64/include/rtems/asm.h | 5 -
.../include/rtems/score/aarch64-system-registers.h | 2 ++
cpukit/score/cpu/aarch64/include/rtems/score/cpu.h | 10 +++---
4 files changed, 18 in
Sebastian Huber (6):
bsps: Add Doxygen group for Arm Generic Timer
aarch64: Add files to Doxygen groups
bsps/aarch64: Define Doxygen groups
bsps/arm: Add Doxygen group for Armv7-M SysTick
bsps/arm: Add CMSIS files to Doxygen group
bsps/arm: Fix Doxygen group assignment
bsps/aarch64
---
bsps/shared/dev/clock/arm-generic-timer.c | 26 ---
1 file changed, 23 insertions(+), 3 deletions(-)
diff --git a/bsps/shared/dev/clock/arm-generic-timer.c
b/bsps/shared/dev/clock/arm-generic-timer.c
index 44cf1ebe6c..b2842df175 100644
--- a/bsps/shared/dev/clock/arm-gene
---
bsps/arm/{ => edb7312}/include/uart.h | 0
spec/build/bsps/arm/edb7312/bspedb7312.yml | 1 +
spec/build/bsps/arm/grp.yml| 1 -
3 files changed, 1 insertion(+), 1 deletion(-)
rename bsps/arm/{ => edb7312}/include/uart.h (100%)
diff --git a/bsps/arm/include/uart.h b/bsps/a
---
spec/build/bsps/arm/csb336/bspcsb336.yml | 3 ++-
spec/build/bsps/arm/csb337/grp.yml | 2 ++
spec/build/bsps/arm/csb337/obj.yml | 1 -
spec/build/bsps/arm/grp.yml | 3 ---
spec/build/bsps/arm/gumstix/bspgumstix.yml | 3 ++-
spec/build/bsps/arm/ob
---
spec/build/bsps/arm/beagle/obj.yml | 5 +
spec/build/bsps/arm/grp.yml| 3 ---
2 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/spec/build/bsps/arm/beagle/obj.yml
b/spec/build/bsps/arm/beagle/obj.yml
index 0f2f354ab9..eaaf09f6ac 100644
--- a/spec/build/bsps/arm/beagle
Sebastian Huber (3):
bsps/arm: Move BSP-specific header file installs
bsps/arm: Use shared object for ARM920 MMU support
bsps/arm: Move BSP-specific header file
bsps/arm/{ => edb7312}/include/uart.h| 0
spec/build/bsps/arm/beagle/obj.yml | 5 +
spec/build/bsps/
This avoids a dependency on memory allocations.
---
bsps/shared/dev/clock/arm-generic-timer.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/bsps/shared/dev/clock/arm-generic-timer.c
b/bsps/shared/dev/clock/arm-generic-timer.c
index ba159f6833..44cf1ebe6c 1006
l mailing list
> devel@rtems.org
> http://lists.rtems.org/mailman/listinfo/devel
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email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
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ly? One option could be to
make the number of interrupt export ports configurable.
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email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht:
Hello,
on which platform does this fix a error?
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email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
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Hallo Joel,
it would be nice to have the interrupt get/set priority directives in
RTEMS 6. When do you want to create the RTEMS 6 branch?
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email: sebastian.hu...@embedded-brains.de
phone: +49-89-1
On 18.04.24 04:02, Chris Johns wrote:
On 17/4/2024 11:06 pm, Sebastian Huber wrote:
Make the kernel I/O output character device processing configurable
through an option set parameter. Add RTEMS_NO_OUTPUT and RTEMS_FLUSH
options. The goal of this API change is to enable flushing the kernel
Make the kernel I/O output character device processing configurable
through an option set parameter. Add RTEMS_NO_OUTPUT and RTEMS_FLUSH
options. The goal of this API change is to enable flushing the kernel
output device in the system termination process before a reset is
issued. A use case for
tatus = arm_interrupt_enable_interrupts();
bsp_interrupt_handler_dispatch_unchecked(vector);
arm_interrupt_restore_interrupts(status);
WRITE_SR(ICC_EOIR1, icciar);
}
}
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email: sebastian.hu...@embedded-brains.de
p
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
---
bsps/sh
On 09.04.24 16:28, Sebastian Huber wrote:
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the directives for the following interrupt
a legacy API, please don't include this header.
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82178 Puchheim
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email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
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Registernu
On 11.04.24 16:56, Kinsey Moore wrote:
Beyond the rebase issue, this patch set looks good.
Thanks for the review, I checked it in.
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Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741
d brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Ras
Make the GIC interrupt controller support a subgroup of the generic interrupt
controller support.
---
bsps/aarch64/include/dev/irq/arm-gic-arch.h| 13 +++--
bsps/arm/include/dev/irq/arm-gic-arch.h| 13 +++--
bsps/include/dev/irq/arm-gic-irq.h | 15 ++
---
bsps/include/bsp/fatal.h | 3 +
bsps/shared/dev/clock/xil-ttc.c | 6 +-
.../bsps/fatal-clock-xil-ttc-irq-install.yml | 21 ++
spec/build/testsuites/validation/grp.yml | 2 +
.../bsps/tr-fatal-clock-xil-ttc-irq-install.c | 187 ++
Sebastian Huber (3):
bsps/xil-ttc: Use interrupt entry
bsps/xil-ttc: Add XIL_FATAL_TTC_IRQ_INSTALL
bsps/xil-ttc: Improve clock driver
bsps/arm/xilinx-zynqmp-rpu/include/bsp.h | 3 -
bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h | 1 -
bsps/include/bsp/fatal.h
---
bsps/shared/dev/clock/xil-ttc.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/bsps/shared/dev/clock/xil-ttc.c b/bsps/shared/dev/clock/xil-ttc.c
index 340c428a48..384f23663b 100644
--- a/bsps/shared/dev/clock/xil-ttc.c
+++ b/bsps/shared/dev/clock/xil-ttc.c
Make the clock driver parameters configurable. Use the maximum counter
frequency to get the best time resolution. Decouple the CPU counter from the
timecounter. Make the tick catch up handling more robust. Add a validation
test for the tick catch up.
---
bsps/arm/xilinx-zynqmp-rpu/include/bsp.
Update #5002.
---
c-user/interrupt/directives.rst | 185 +-
c-user/interrupt/introduction.rst | 10 +-
c-user/rtems_data_types.rst | 19 ++-
3 files changed, 211 insertions(+), 3 deletions(-)
diff --git a/c-user/interrupt/directives.rst b/c-user/interrupt/dir
Add directives to get and set the priority of an interrupt vector.
Implement the directives for the following BSP families:
* arm/lpc24xx
* arm/lpc32xx
* powerpc/mpc55xxevb
* powerpc/qoriq
Implement the directives for the following interrupt controllers:
* GICv2 and GICv3 (arm and aarch64)
* NV
On 09.04.24 14:41, Joel Sherrill wrote:
Is 14 the version for RTEMS 7 tools? If so, that makes it easier to
address the issues.
I don't have time to update the RTEMS 7 tools currently.
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germ
Hello,
I did some tests with GCC 14 and it turned out that this release turns a
couple of warnings into errors:
https://gcc.gnu.org/gcc-14/porting_to.html
It will be a bit of work to get RTEMS compile clean for GCC 14.
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Herr Sebastian HUBER
Dornierst
The powerpc context switch restores the interrupt state.
Update #4955.
---
testsuites/validation/tc-score-isr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/testsuites/validation/tc-score-isr.c
b/testsuites/validation/tc-score-isr.c
index 9891829a84..b178541e72 100644
---
The processor mask implementation uses flsl() from which is
only BSD visible. Move the implementation to a separate header file to
hide it from the API level. This fixes build errors with GCC 14.
---
cpukit/include/rtems/score/processormask.h| 379 +--
.../include/rtems/score/pr
In addtion to 1023, the GICC_IAR register may return 1022 as a special value.
Simply check for a valid interrupt vector for the dispatching.
Check the GICC_IAR again after the dispatch to quickly process a next interrupt
without having to go through the interrupt prologue and epiloge.
---
bsps/aa
On the arm target, __udivmoddi4() cannot be fully tested through normal
integer divisions.
Update #3716.
---
testsuites/unit/tc-compiler-builtins.c | 221 +++--
1 file changed, 207 insertions(+), 14 deletions(-)
diff --git a/testsuites/unit/tc-compiler-builtins.c
b/testsuite
Make sure that the last IPI is processed before the next test case is
carried out.
---
testsuites/smptests/smpipi01/init.c | 48 +
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/testsuites/smptests/smpipi01/init.c
b/testsuites/smptests/smpipi01/init.c
i
Add directives to get and set the priority of an interrupt vector.
Update #5002.
---
cpukit/include/rtems/rtems/intr.h | 154 +-
1 file changed, 153 insertions(+), 1 deletion(-)
diff --git a/cpukit/include/rtems/rtems/intr.h
b/cpukit/include/rtems/rtems/intr.h
index
these two currently independent drivers.
--
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Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
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Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
---
bsps/aarch64/xilinx-zynqmp/console/console.c | 41 ++
bsps/arm/xilinx-zynq/console/console-config.c | 50
This helps to provide a shared implementation of the kernel I/O support.
---
bsps/aarch64/xilinx-zynqmp/console/console.c | 4 +-
bsps/aarch64/xilinx-zynqmp/include/bsp.h | 2 +
bsps/arm/xilinx-zynq/console/console-config.c | 5 +-
bsps/arm/xilinx-zynq/include/bsp.h| 1 +
...
Make the initialization and polled functions independent of the Termios
context. This helps to implement the kernel I/O support without a dependency
on the Termios framework.
---
bsps/aarch64/xilinx-zynqmp/console/console.c | 23 ---
bsps/arm/xilinx-zynq/console/debug-console.c | 15
GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
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);
#else
Thanks, I checked it in.
--
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
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Registernummer: HRB 15
On 25.03.24 21:36, Bernd Moessner wrote:
On 25.03.2024 13:26, Sebastian Huber wrote:
Hello,
the BSPs for the Xilinx Zynq/ZynqMP/Versal platforms use code from
Xilinx. They also install some header files from Xilinx in the
top-level include directory of the BSP, for example:
sleep.h
Add a multilib with workarounds for Cortex-A53 errata.
gcc/ChangeLog:
* config.gcc (aarch64-*-rtems*): Add target makefile fragment
t-aarch64-rtems.
* config/aarch64/t-aarch64-rtems: New file.
---
gcc/config.gcc | 1 +
gcc/config/aarch64/t-aarch64-rte
brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernummer: HRB 157899
Vertretungsberechtigte Geschäftsführer: Peter Rasmu
gcc/ChangeLog:
* config.gcc (aarch64-*-rtems*): Add target makefile fragment
t-aarch64-rtems.
* config/aarch64/t-aarch64-rtems: New file.
---
gcc/config.gcc | 1 +
gcc/config/aarch64/t-aarch64-rtems | 41 ++
2 files changed,
http://devel.rtems.org/ticket/5003
Do we need an ILP32 multilib for Cortex-A53?
--
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Am
GICv3, ...
I added those questions to the ticket also.
Gedare
On Wed, Mar 20, 2024 at 2:59 AM Sebastian Huber
wrote:
Hello,
I added a ticket for a proposal for an API to get and set interrupt
priorities for interrupt vectors:
https://devel.rtems.org/ticket/5002
I would like to implement this A
pplication depending on the system configuration.
--
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsgericht München
Registernumm
having specific BSPs. The
customization can be done through BSP options and a device tree. The
only thing we need are the right compiler options.
--
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89
have to enable some
errata workarounds:
https://devel.rtems.org/ticket/5003
--
embedded brains GmbH & Co. KG
Herr Sebastian HUBER
Dornierstr. 4
82178 Puchheim
Germany
email: sebastian.hu...@embedded-brains.de
phone: +49-89-18 94 741 - 16
fax: +49-89-18 94 741 - 08
Registergericht: Amtsger
---
cpukit/include/rtems/score/basedefs.h | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/cpukit/include/rtems/score/basedefs.h
b/cpukit/include/rtems/score/basedefs.h
index 4f28e6a525..010728d795 100644
--- a/cpukit/include/rtems/score/basedefs.h
+++ b/cpukit/inc
Make the initialization and polled functions independent of the Termios
context. This helps to implement the kernel I/O support without a dependency
on the Termios framework.
---
bsps/aarch64/xilinx-zynqmp/console/console.c | 23 ---
bsps/arm/xilinx-zynq/console/debug-console.c | 15
Replace the BSP_CONSOLE_MINOR BSP option for the Xilinx Zynq BSPs with the new
BSP option ZYNQ_UART_KERNEL_IO_BASE_ADDR. Move the kernel I/O support to a
shared file.
---
bsps/aarch64/xilinx-zynqmp/console/console.c | 41 ++
bsps/arm/xilinx-zynq/console/console-config.c | 50
This helps to provide a shared implementation of the kernel I/O support.
---
bsps/aarch64/xilinx-zynqmp/console/console.c | 4 ++--
bsps/arm/xilinx-zynq/console/console-config.c | 5 +++--
.../console/console-config.c | 4 ++--
.../xilinx-zynqmp/console/console-config.c|
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