[PATCH rtems-libbsd v2 2/2] freebsd/cgem: Read clock frequency from device tree

Read the clock frequency from the device tree and use it to calculate the mdc clock divider for the MII bus if not found then use default clock divider. --- freebsd/sys/dev/cadence/if_cgem.c | 42 --- 1 file changed, 39 insertions(+), 3 deletions(-) diff --git a/freebs

[PATCH rtems-libbsd v2 1/2] freebsd/cgem: Add phy address to read it from device tree

Read the phy address from the device tree and use it to find the phy device if not found then search in the range of 0 to 31. --- freebsd/sys/dev/cadence/if_cgem.c | 30 ++ 1 file changed, 30 insertions(+) diff --git a/freebsd/sys/dev/cadence/if_cgem.c b/freebsd/sys/d

[PATCH rtems-libbsd v2 0/2] Update the CGEM driver

changes gated behind #ifdef __rtems__ - Use braces {} with if/else for a single line - Drop weak symbol patch Padmarao Begari (2): freebsd/cgem: Add phy address to read it from device tree freebsd/cgem: Read clock frequency from device tree freebsd/sys/dev/cadence/if_cgem.c | 72

[PATCH rtems-libbsd] nexus-devices: Add riscv/MPFS BSP variant

Add riscv Microchip PolarFire SoC BSP variant and the CGEM driver support --- rtemsbsd/include/bsp/nexus-devices.h | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/rtemsbsd/include/bsp/nexus-devices.h b/rtemsbsd/include/bsp/nexus-devices.h index 43a08207..239cb21e

[PATCH rtems-libbsd 3/3] freebsd/cgem: Add weak symbol for riscv

Add __weak_symbol instead of __weak_reference for the cgem_set_ref_clk() function for riscv build. --- freebsd/sys/dev/cadence/if_cgem.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/freebsd/sys/dev/cadence/if_cgem.c b/freebsd/sys/dev/cadence/if_cgem.c index 363a9717..a12f7b43 100644

[PATCH rtems-libbsd 2/3] freebsd/cgem: Read clock frequency from device tree

Read the clock frequency from the device tree and use it to calculate the mdc clock divider for the MII bus if not found then use default clock divider. --- freebsd/sys/dev/cadence/if_cgem.c | 39 --- 1 file changed, 36 insertions(+), 3 deletions(-) diff --git a/freebs

[PATCH rtems-libbsd 1/3] freebsd/cgem: Add phy address to read it from device tree

Read the phy address from the device tree and use it to find the phy device if not found then search in the range of 0 to 31. --- freebsd/sys/dev/cadence/if_cgem.c | 41 --- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/freebsd/sys/dev/cadence/if_cgem.c

[PATCH rtems-libbsd 0/3] Update the CGEM driver

1aa4cb8568594aa54238c9fbf2cc0f3ea4edec7f Padmarao Begari (3): freebsd/cgem: Add phy address to read it from device tree freebsd/cgem: Read clock frequency from device tree freebsd/cgem: Add weak symbol for riscv freebsd/sys/dev/cadence/if_cgem.c | 87 --- 1 file changed, 80

[PATCH Resend] bsps/riscv: Clear interrupt complete before disable

The interrupt complete should clear with the interrupt number before disabling the interrupt in the PLIC to get the next interrupt. --- bsps/riscv/riscv/irq/irq.c | 4 1 file changed, 4 insertions(+) diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index e8d297052b..8e72b

[PATCH] bsps/riscv: Clear interrupt complete before disable

The interrupt complete should clear with the interrupt number before disabling the interrupt in the PLIC to get the next interrupt. --- bsps/riscv/riscv/irq/irq.c | 4 1 file changed, 4 insertions(+) diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index e8d297052b..8e72b

[PATCH rtems-docs v2] user/bsps: Update riscv for PolarFire SoC

Update the riscv documentation for the Microchip PolarFire SoC BSP variant including information about SMP test procedure for the Microchip PolarFire Icicle Kit. --- user/bsps/bsps-riscv.rst | 126 ++- 1 file changed, 125 insertions(+), 1 deletion(-) diff --git

[PATCH rtems-docs] user/bsps: Update riscv for PolarFire SoC

Update the riscv documentation for the Microchip PolarFire SoC BSP variant including information about SMP test procedure for the Microchip PolarFire Icicle Kit. --- user/bsps/bsps-riscv.rst | 114 ++- 1 file changed, 113 insertions(+), 1 deletion(-) diff --git

[PATCH v2 2/4] spec/build/bsps: Add dtb support

Add dtb and dtb header path configurable build option --- spec/build/bsps/optdtb.yml | 19 +++ spec/build/bsps/optdtbheaderpath.yml | 20 2 files changed, 39 insertions(+) create mode 100644 spec/build/bsps/optdtb.yml create mode 100644 spec/build/b

[PATCH v2 1/4] bsps/riscv: Add device tree blob

: BSD-2-Clause */ + +/* + * Copyright (C) Padmarao Begari + * Copyright (C) 2022 Microchip Technology Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source

[PATCH v2 4/4] bsps/shared/: Use device tree blob

If the bsp is integrated and supported a device tree blob(dtb) then use dtb instead of using it from the U-Boot (BSP_START_COPY_FDT_FROM_U_BOOT=False). --- bsps/shared/start/bsp-fdt.c | 8 1 file changed, 8 insertions(+) diff --git a/bsps/shared/start/bsp-fdt.c b/bsps/shared/start/bsp-fd

[PATCH v2 3/4] bsps/riscv: Add Microchip PolarFire SoC BSP variant

The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART. --- bsps/riscv/riscv/clock/clockdrv.c

[PATCH v2 0/4] Microchip PolarFire SoC support

RTEMS_BOOT_HARDID - Add '_RISCV_Map_hardid_to_cpu_index()' and '_RISCV_Map_cpu_index_to_hardid()' functions - Change bsp_fdt_get() instead of bsp_fdt_copy() function for dtb - Move dtb and dtb header configurable build option to the bsps Padmarao Begari (4): bsps/riscv: Add device tree bl