[PATCH] cpukit/riscv : RISCV multitasking with non SMP

Modification of RISCV multitasking in case of non SMP configuration (single core). The previous RISC-V multitasking implementation was not functionnal in case of non-SMP configuration. This modification implement the _RISCV_Start_multitasking function even if the SMP flag is disabled. --- Here i

[PATCH 3/3] Force ISR enable before scheduler start

The ISR was not activated when running without RTEMS_SMP. --- cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 3 +++ cpukit/score/cpu/riscv/riscv-context-switch.S| 5 + cpukit/score/src/threadstartmultitasking.c | 2 +- 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a

[PATCH 2/3] bsps/riscv: Handle ":" in chosen stdout-path

The riscv_get_console_node function is searching the devices for the string specified in chosen in the fdt. Unfortunately, this chosen string can contain parameters after the ":" character. As specified in https://www.kernel.org/doc/Documentation/devicetree/bindings/chosen.txt : If the char

[PATCH 1/3] Adding core-v cv32a6 support

This commit add support for the CV32A6 processor in the rv32imac configuration. The CORE-V CVA6 is an application class 6 stage RISC-V CPU capable of booting Linux. It support multiple configurations : ISA (IMACFDB), XLEN 32 and 64, configurable cache size, TLBs, PTW and branch prediction. It is