Modification of RISCV multitasking in case of non SMP configuration (single
core).
The previous RISC-V multitasking implementation was not functionnal in case of
non-SMP configuration.
This modification implement the _RISCV_Start_multitasking function even if the
SMP flag is disabled.
---
Here is a modified patch for ISR activation on RISC-V single core. I still do
not understand why RTEMS forbid multitask on single core.
Without this modification, I observe errors in the _Thread_Do_dispatch function
at _ISR_Is_enabled check as ISR is not enabled in single core.
I have made some tests with multitask queues and semaphore, they seem to work.
This patch affect only RISC-V architecture.
cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 4 ++--
cpukit/score/cpu/riscv/riscv-context-switch.S | 8 ++++++--
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
index f74ce99684..e6fd40d2b5 100644
--- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
+++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h
@@ -499,12 +499,12 @@ static inline void _CPU_Context_Set_is_executing(
context->is_executing = is_executing;
}
+#endif /* RTEMS_SMP */
+
RTEMS_NO_RETURN void _RISCV_Start_multitasking( Context_Control *heir );
#define _CPU_Start_multitasking( _heir ) _RISCV_Start_multitasking( _heir )
-#endif /* RTEMS_SMP */
-
/** Type that can store a 32-bit integer or a pointer. */
typedef uintptr_t CPU_Uint32ptr;
diff --git a/cpukit/score/cpu/riscv/riscv-context-switch.S
b/cpukit/score/cpu/riscv/riscv-context-switch.S
index cfaff444b0..d6424c9d49 100644
--- a/cpukit/score/cpu/riscv/riscv-context-switch.S
+++ b/cpukit/score/cpu/riscv/riscv-context-switch.S
@@ -40,9 +40,7 @@
PUBLIC(_CPU_Context_switch)
PUBLIC(_CPU_Context_switch_no_return)
PUBLIC(_CPU_Context_restore)
-#ifdef RTEMS_SMP
PUBLIC(_RISCV_Start_multitasking)
-#endif
SYM(_CPU_Context_switch):
SYM(_CPU_Context_switch_no_return):
@@ -190,4 +188,10 @@ SYM(_RISCV_Start_multitasking):
csrrs zero, mstatus, RISCV_MSTATUS_MIE
j .Ltry_update_is_executing
+#else
+SYM(_RISCV_Start_multitasking):
+ /* Enable interrupts */
+ csrrs zero, mstatus, RISCV_MSTATUS_MIE
+
+ j _CPU_Context_restore
#endif
--
2.25.1
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