Re: [PATCH 1/2] bsps/include/libchip: Remove legacy networking header file

copied to rtems-net-legacy but not deleted here. On Mon, Nov 14, 2022 at 2:50 AM Daniel Cederman wrote: --- bsps/include/libchip/greth.h | 152 --- 1 file changed, 152 deletions(-) delete mode 100644 bsps/include/libchip/greth.h diff --git a/bsps/include/libchip

[PATCH 6/6] testsuites/smptests: Change license to BSD-2 for files with Gaisler copyright

This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Updates #3053. --- testsuites/smptests/smpcapture02/init.c | 25 ++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --gi

[PATCH 5/6] cpukit: Change license to BSD-2 for files with Gaisler copyright

This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053. --- cpukit/include/drvmgr/d

[PATCH 3/6] bsps/sparc: Change license to BSD-2 for files with Gaisler copyright

This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053. --- bsps/sparc/erc32/includ

[PATCH 4/6] bsps/riscv: Change license to BSD-2 for files with Gaisler copyright

This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053. --- bsps/riscv/griscv/clock

[PATCH 2/6] bsps/shared/grlib: Change license to BSD-2 for files with Gaisler copyright

This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053. --- bsps/shared/grlib/1553/

[PATCH 1/6] bsps/include/grlib: Change license to BSD-2 for files with Gaisler copyright

This patch changes the license to BSD-2 for all source files where the copyright is held by Aeroflex Gaisler, Cobham Gaisler, or Gaisler Research. Some files also includes copyright right statements from OAR and/or embedded Brains in addition to Gaisler. Updates #3053. --- bsps/include/grlib/ahbs

[PATCH 1/2] bsps/include/libchip: Remove legacy networking header file

--- bsps/include/libchip/greth.h | 152 --- 1 file changed, 152 deletions(-) delete mode 100644 bsps/include/libchip/greth.h diff --git a/bsps/include/libchip/greth.h b/bsps/include/libchip/greth.h deleted file mode 100644 index c6e000dbd3..00 --- a/bsps/i

[PATCH 2/2] user: Add documentation for leon2 and leon3 BSP

--- user/bsps/bsps-sparc.rst | 74 ++-- 1 file changed, 72 insertions(+), 2 deletions(-) diff --git a/user/bsps/bsps-sparc.rst b/user/bsps/bsps-sparc.rst index d0316a9..a2c2a47 100644 --- a/user/bsps/bsps-sparc.rst +++ b/user/bsps/bsps-sparc.rst @@ -20,11 +20,8

[PATCH 1/2] user: Add documentation for NOEL-V BSP

--- user/bsps/bsps-riscv.rst | 57 1 file changed, 57 insertions(+) diff --git a/user/bsps/bsps-riscv.rst b/user/bsps/bsps-riscv.rst index 48e7ee7..73a6038 100644 --- a/user/bsps/bsps-riscv.rst +++ b/user/bsps/bsps-riscv.rst @@ -248,6 +248,63 @@ Serial ter

[PATCH v6 1/1] bsp/riscv: Add NOEL-V BSP

From: Martin Aberg Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the followi

[PATCH v6 0/1] NOEL-V BSP

v6 Change family entry to noel in all BSP build specs Synchronize irq.h and riscv.h with versions in riscv BSP Martin Aberg (1): bsp/riscv: Add NOEL-V BSP bsps/include/bsp/fatal.h | 3 + bsps/riscv/noel/console/console-config.c | 208 ++ bsps/riscv/n

Re: [PATCH v5 0/1] NOEL-V BSP

e yet. --joel On Tue, Aug 30, 2022 at 6:39 AM Daniel Cederman wrote: Hi, Is it OK to push this or should I wait for additional comments? On 2022-08-25 10:33, Daniel Cederman wrote: v5 Made RISCV_CONSOLE_MAX_APBUART_DEVICES an option bsp_fatal if no uart clock frequen

Re: [PATCH v5 1/1] bsp/riscv: Add NOEL-V BSP

On 2022-08-30 21:04, Sebastian Huber wrote: On 25/08/2022 10:33, Daniel Cederman wrote: +#define BSP_INTERRUPT_VECTOR_MIN 0 + +#define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1) I am a bit surprised that this worked, since the API changed

Re: [PATCH v5 0/1] NOEL-V BSP

Hi, Is it OK to push this or should I wait for additional comments? On 2022-08-25 10:33, Daniel Cederman wrote: v5 Made RISCV_CONSOLE_MAX_APBUART_DEVICES an option bsp_fatal if no uart clock frequency is found Changed CONSOLE_USE_INTERRUPTS to BSP_CONSOLE_USE_INTERRUPTS Added error codes for

[PATCH v5 1/1] bsp/riscv: Add NOEL-V BSP

From: Martin Aberg Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the followi

[PATCH v5 0/1] NOEL-V BSP

v5 Made RISCV_CONSOLE_MAX_APBUART_DEVICES an option bsp_fatal if no uart clock frequency is found Changed CONSOLE_USE_INTERRUPTS to BSP_CONSOLE_USE_INTERRUPTS Added error codes for APBUART Get work area size from /memory node Martin Aberg (1): bsp/riscv: Add NOEL-V BSP bsps/include/bsp/fatal.h

[PATCH 2/2] tester: Load RISC-V image using -bios and increase memory size

This avoids overlapping the RTEMS image with the builtin opensbi image and the location of the fdt. --- tester/rtems/testing/bsps/rv64imafd_medany.ini | 3 ++- tester/rtems/testing/bsps/rv64imafdc_medany.ini | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tester/rtems/test

[PATCH 1/2] tester: Add option to specify how to load image with QEMU

Defaults to "-kernel", but can be changed to, for example, "-bios". --- tester/rtems/testing/qemu.cfg | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/tester/rtems/testing/qemu.cfg b/tester/rtems/testing/qemu.cfg index 3c51bee..0b592ef 100644 --- a/tester/rtems/testing/qemu.

Re: [PATCH v2 1/1] bsp/riscv: Work area size based on /memory node in fdt

On 2022-08-19 11:16, Hesham Almatary wrote: On Thu, 18 Aug 2022 at 13:55, Daniel Cederman wrote: I missed your comment, but have made the change now. Are there any instructions on how to run the RISCV BSP tests on QEMU or Spike? I could not get it to work. Do I need a special version of QEMU

Re: [PATCH v2 1/1] bsp/riscv: Work area size based on /memory node in fdt

t;end == 0" with "end == NULL" as per my comment above. Also please test on other RISC-V QEMU platforms to make sure nothing got broken. On Wed, 17 Aug 2022 at 14:10, Joel Sherrill wrote: I'm ok with this if Hesham acks as well. --joel On Wed, Aug 17, 2022 at 6:35 AM Daniel Ce

[PATCH v2 1/1] bsp/riscv: Work area size based on /memory node in fdt

Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node. --- bsps/riscv/shared/start/bspgetworkarea.c | 144 +++ spec/build/bsps/riscv/riscv/obj.yml | 1 + 2 files changed, 145 insertions(+)

Re: [PATCH] bsp/riscv: Work area size based on /memory node in fdt

Sure, I can move it to the shared directory (riscv/shared/start). On 2022-08-17 11:16, Hesham Almatary wrote: Thanks for the patch. LGTM. I wonder if we can also reuse that for the generic shared RISC-V BSP (e.g., bsps/riscv/riscv) instead of just NOEL? On Wed, 17 Aug 2022 at 09:58, Daniel

[PATCH] bsp/riscv: Work area size based on /memory node in fdt

Uses the first entry in the /memory node to determine the end of the work area. Falls back on linker symbol if unable to parse the node. --- bsps/riscv/noel/start/bspgetworkarea.c | 144 + spec/build/bsps/riscv/noel/obj.yml | 1 + 2 files changed, 145 insertions(+) c

Re: [PATCH v4 1/2] bsp/riscv: Work area size based on stack pointer

On 2022-08-15 17:19, Hesham Almatary wrote: On Mon, 15 Aug 2022 at 15:35, Daniel Cederman wrote: On 2022-08-15 15:43, Hesham Almatary wrote: On Mon, 15 Aug 2022 at 08:16, Daniel Cederman wrote: From: Martin Aberg Remember the initial stack pointer in start.S. It can later be used to

Re: [PATCH v4 1/2] bsp/riscv: Work area size based on stack pointer

On 2022-08-15 15:43, Hesham Almatary wrote: On Mon, 15 Aug 2022 at 08:16, Daniel Cederman wrote: From: Martin Aberg Remember the initial stack pointer in start.S. It can later be used to determine top of RAM. --- bsps/riscv/include/bsp/start.h| 67

[PATCH v4 1/2] bsp/riscv: Work area size based on stack pointer

From: Martin Aberg Remember the initial stack pointer in start.S. It can later be used to determine top of RAM. --- bsps/riscv/include/bsp/start.h| 67 .../shared/start/bspgetworkarea-fromstack.c | 76 +++ bsps/riscv/shared/start/start.S

[PATCH v4 2/2] bsp/riscv: Add NOEL-V BSP

From: Martin Aberg Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the followi

[PATCH v4 0/2] NOEL-V BSP

v4 Changed .data to .bsp_start_data Moved assembly defines to asm.h Use the common optextirqmax Use optconsoleirq instead of optconirq Declared riscv_start_stack_pointer as const Martin Aberg (2): bsp/riscv: Work area size based on stack pointer bsp/riscv: Add NOEL-V BSP bsps/riscv/include/b

[PATCH v3 2/2] bsp/riscv: Add NOEL-V BSP

From: Martin Aberg Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the followi

[PATCH v3 1/2] bsp/riscv: Work area size based on stack pointer

From: Martin Aberg Remember the initial stack pointer in start.S. It can later be used to determine top of RAM. --- bsps/riscv/include/bsp/start.h| 67 .../shared/start/bspgetworkarea-fromstack.c | 76 +++ bsps/riscv/shared/start/start.S

[PATCH v3 0/2] NOEL-V BSP

Thanks Joel, I have updated the license information. Martin Aberg (2): bsp/riscv: Work area size based on stack pointer bsp/riscv: Add NOEL-V BSP bsps/riscv/include/bsp/start.h| 67 ++ bsps/riscv/noel/console/console-config.c | 209 ++ bsps/riscv/noe

[PATCH v2 2/2] bsp/riscv: Add NOEL-V BSP

From: Martin Aberg Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the followi

[PATCH v2 1/2] bsp/riscv: Work area size based on stack pointer

From: Martin Aberg Remember the initial stack pointer in start.S. It can later be used to determine top of RAM. --- bsps/riscv/include/bsp/start.h| 65 +++ .../shared/start/bspgetworkarea-fromstack.c | 53 +++ bsps/riscv/shared/start/start.S

[PATCH v2 0/2] NOEL-V BSP

Thank you Sebastian for reviewing the patches. I have updated them according to your comments. Martin Aberg (2): bsp/riscv: Work area size based on stack pointer bsp/riscv: Add NOEL-V BSP bsps/riscv/include/bsp/start.h| 65 ++ bsps/riscv/noel/console/console-config.c

[PATCH 5/5] bsp/riscv: Add NOEL-V configuration files

From: Martin Aberg --- bsps/riscv/noel/config/noel32im.cfg | 9 + bsps/riscv/noel/config/noel32imafd.cfg | 9 + bsps/riscv/noel/config/noel64imac.cfg | 9 + bsps/riscv/noel/config/noel64imafd.cfg | 9 + bsps/riscv/noel/config/noel64imafdc.cfg | 9 +

[PATCH 4/5] bsp/riscv: Add NOEL-V BSP build specification

From: Martin Aberg --- spec/build/bsps/riscv/noel/abi.yml| 48 +++ spec/build/bsps/riscv/noel/bspnoel32im.yml| 19 ++ spec/build/bsps/riscv/noel/bspnoel32imafd.yml | 19 ++ spec/build/bsps/riscv/noel/bspnoel64imac.yml | 19 ++ spec/build/bsps/riscv/noel/b

[PATCH 3/5] bsp/riscv: Work area size based on stack pointer

From: Martin Aberg Remember the initial stack pointer in start.S. It can later be used to determine top of RAM. --- bsps/riscv/include/bsp/start.h| 65 +++ .../shared/start/bspgetworkarea-fromstack.c | 53 +++ bsps/riscv/shared/start/start.S

[PATCH 2/5] bsp/riscv: Add NOEL-V BSP

From: Martin Aberg Added support for Cobham Gaisler NOEL-V systems. The NOEL-V support is implemented as a riscv BSP. Both 32-bit and 64-bit processor systems are supported. Cobham Gaisler's NOEL-V RISC-V processor IP is described here: https://www.gaisler.com/NOELV Compatible with the followi

[PATCH 0/5] NOEL-V BSP

Hello, This patch set adds support for the NOEL-V RISC-V processors. Currently there is a problem linking the ts-validation-cache.exe test for 64-bit configurations. It fails with the following error message: bsps/riscv/shared/start/start.S:100:(.bsp_start_text+0x70): relocation truncated to fit

[PATCH 1/5] apbuart_termios: use bsp/irq.h

From: Martin Aberg The real dependency in this case is on rtems/irq-extension.h. The theme in other other console drivers is to get it via bsp/irq.h, so that pattern is followed. --- bsps/shared/grlib/uart/apbuart_termios.c | 1 + 1 file changed, 1 insertion(+) diff --git a/bsps/shared/grlib/ua

Re: sparc-rtems5-gcc Internal Compiler Error

Hi Joel, Yes, there was a bug in one of the errata fixes. It has been fixed now, see https://gcc.gnu.org/ml/gcc-patches/2017-12/msg00593.html and https://devel.rtems.org/ticket/3242#comment:4. Daniel C On 2017-12-19 16:18, Joel Sherrill wrote: Hi Has anyone else seen this? sparc-rtems5-gc

Re: [PATCH] sparc: Rename NGMP to GR740 and add configs for UT699, UT700, and GR712RC

On 2017-07-14 14:02, Sebastian Huber wrote: Could you please point me to the relevant thread on the mailing list? No, this was just something I was told. If you do not recognize it I might have misunderstood. -- Daniel Cederman Software Engineer Cobham Gaisler

[PATCH-v2] sparc: Rename NGMP to GR740 and add configs for UT699, UT700, and GR712RC

The UT699 requires -mcpu=leon as it does not support the CAS instruction provided by -mcpu=leon3. It also requires -mfix-ut699 for errata fixes. UT700 and GR712RC requires the -mfix-ut700 and -mfix-gr712rc flags that have been recently added to GCC's master and 7-branch. Remove -msoft-float from

Re: [PATCH] sparc: Rename NGMP to GR740 and add configs for UT699, UT700, and GR712RC

like a good idea. I will revise my patch and remove -msoft-float. -- Daniel Cederman Software Engineer Cobham Gaisler ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: [PATCH] sparc: Rename NGMP to GR740 and add configs for UT699, UT700, and GR712RC

only being saved if the last FP task was switched out as the result of an interrupt? And similar for loading the FP context? No need to load it if returning from a call to rtems_task_wake_after() I guess. -- Daniel Cederman Software Engineer Cobham Gaisler

Re: [PATCH] sparc: Rename NGMP to GR740 and add configs for UT699, UT700, and GR712RC

detected by probing. So in RCC hard floats have always been used if the hardware supports it, as I understand it. I could revise the patch to remove the -msoft-flag as, as you say, most people would like to use hard floats. -- Daniel Cederman Software Engineer Cobham Gaisler

[PATCH] sparc: Rename NGMP to GR740 and add configs for UT699, UT700, and GR712RC

The UT699 requires -mcpu=leon as it does not support the CAS instruction provided by -mcpu=leon3. It also requires -mfix-ut699 for errata fixes. UT700 and GR712RC requires the -mfix-ut700 and -mfix-gr712rc flags that have been recently added to GCC's master and 7-branch. --- c/src/lib/libbsp/spar

[PATCH] sparc: Add assembly workaround for LEON3FT B2BST errata

This patch adds NOP instructions to prevent instruction sequences that are sensitive to the LEON3FT B2BST errata. See GRLIB-TN-0009: "LEON3FT Stale Cache Entry After Store with Data Tag Parity Error" for more information. The sequences are only modified if __FIX_LEON3FT_B2BST is defined. The patc

Re: [PATCH-V4 1/1] sparc: Fix context switch on SMP

Great, thanks! On 2015-11-17 09:01, Sebastian Huber wrote: Thanks, I check in this patch on the 4.11 branch. -- Daniel Cederman Software Engineer Cobham Gaisler ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

[PATCH-V4 1/1] sparc: Fix context switch on SMP

We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first wri

Re: [PATCH-V3 1/1] sparc: Fix context switch on SMP

Yes, definitely. Would you mind doing it? Daniel is away from office this week and I do not have access. On 2015-11-16 15:57, Sebastian Huber wrote: Looks good, we should probably apply it to the 4.11 branch as well. -- Daniel Cederman Software Engineer Cobham Gaisler

[PATCH-V3 1/1] sparc: Fix context switch on SMP

We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first wri

Re: [PATCH-V2 1/1] sparc: Fix context switch on SMP

Ok, then I will remove that line. I like the assert idea and will add that to the patch. Thank you for your comments and help! On 2015-11-16 13:52, Sebastian Huber wrote: On 16/11/15 13:14, Daniel Cederman wrote: I was unsure if the ET bit was always set or not for newly created task contexts

Re: [PATCH-V2 1/1] sparc: Fix context switch on SMP

I was unsure if the ET bit was always set or not for newly created task contexts, or if this was the first place that traps got enabled for a new task. If it is always set we can remove that instruction. On 2015-11-16 11:27, Sebastian Huber wrote: On 16/11/15 11:06, Daniel Cederman wrote

[PATCH-V2 1/1] sparc: Fix context switch on SMP

We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. With this patch the write to PSR is divided into two steps. We first update the current window pointer and then we restore the status registers and enable traps. This allows us to move the first wri

[PATCH 1/1] sparc: Fix context switch on SMP

We must not load registers (e.g. PSR) from the heir context area before the heir stopped execution. --- c/src/lib/libbsp/sparc/shared/irq_asm.S | 30 +- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/

Re: PSR register not getting updated

When I think a bit more of it, one probably should update the PSR after the heir has been acquired, as the task could potentially be acquired and released again with a new PSR by another core before the swap. On 2015-11-12 11:27, Daniel Cederman wrote: Hello, I experienced a bug when using

[PATCH 1/1] sparc: Update PSR register when heir changes

The PSR register holds condition codes, the FPU enable bit, and similar, which needs to be restored properly when switching task. --- c/src/lib/libbsp/sparc/shared/irq_asm.S | 8 1 file changed, 8 insertions(+) diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S b/c/src/lib/libbsp/spar

PSR register not getting updated

. -- Daniel Cederman Software Engineer Cobham Gaisler F : +46 (0) 31 421407 daniel.ceder...@gaisler.com ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

[PATCH] smptests/smpcache01: Enable interrupts before waiting for other CPUs

Otherwise there is a risk that a CPU misses a cache manager message from another CPU and the test hangs. --- testsuites/smptests/smpcache01/init.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/testsuites/smptests/smpcache01/init.c b/testsuites/smptests/smpcache01/init.c

[PATCH 2/2] posix: Return error code if mmap is used

--- cpukit/posix/src/mmap.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cpukit/posix/src/mmap.c b/cpukit/posix/src/mmap.c index 3ebb2f4..90c6d0a 100644 --- a/cpukit/posix/src/mmap.c +++ b/cpukit/posix/src/mmap.c @@ -26,5 +26,5 @@ void *mmap( off_t off ) { - return N

[PATCH 1/2] posix: Move function to file with matching name

mmap was previously in munmap.c and munmap was in mmap.c. --- cpukit/posix/src/mmap.c | 10 +++--- cpukit/posix/src/munmap.c | 10 +++--- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/cpukit/posix/src/mmap.c b/cpukit/posix/src/mmap.c index 2798326..3ebb2f4 100644 --- a

[PATCH] rtems: Use atomic operation with correct type

--- c/src/lib/libcpu/shared/src/cache_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index 7ff1166..89ec88f 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src

Re: [rtems commit] smpcapture02: Add test of functionality to add custom entries to capture trace

ttp://git.rtems.org/rtems/commit/?id=8d8573acc8f620c93afa8dd30ea8418d25ad2d21 Author:Daniel Cederman Date: Wed Feb 4 10:04:05 2015 +0100 smpcapture02: Add test of functionality to add custom entries to capture trace -- Daniel Cederman Software Engineer Cobham Gaisler daniel.ceder...@

Re: [rtems commit] smpcapture02: Add test of functionality to add custom entries to capture trace

fa8dd30ea8418d25ad2d21 Author:Daniel Cederman Date: Wed Feb 4 10:04:05 2015 +0100 smpcapture02: Add test of functionality to add custom entries to capture trace --- testsuites/smptests/Makefile.am | 1 + testsuites/smptests/configure.ac | 1 +

Re: [PATCH] bsp/sparc: Move BSP_ISR_handler to a separate file

lawyer. -Gedare On Wed, Feb 4, 2015 at 4:52 AM, Daniel Cederman wrote: This allows it to be wrapped by another function at link-time and can be used to trace interrupts. If not placed in a separate file, the function pointer address used in BSP_shared_interrupt_init will be resolved at compile-time

[PATCH 2/2] doc: Document network task affinity option

--- doc/networking/networkapp.t | 14 ++ 1 file changed, 14 insertions(+) diff --git a/doc/networking/networkapp.t b/doc/networking/networkapp.t index 62b1a53..dd356a8 100644 --- a/doc/networking/networkapp.t +++ b/doc/networking/networkapp.t @@ -101,6 +101,11 @@ struct rtems_bsdnet_c

[PATCH] grspw: Fix typos

--- c/src/lib/libbsp/sparc/shared/spw/grspw.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/c/src/lib/libbsp/sparc/shared/spw/grspw.c b/c/src/lib/libbsp/sparc/shared/spw/grspw.c index d3eb9b9..d869d17 100644 --- a/c/src/lib/libbsp/sparc/shared/spw/grspw.c +++ b/c/src/l

[PATCH] smpcapture02: Add test of functionality to add custom entries to capture trace

--- testsuites/smptests/Makefile.am | 1 + testsuites/smptests/configure.ac | 1 + testsuites/smptests/smpcapture02/Makefile.am | 19 + testsuites/smptests/smpcapture02/init.c | 425 ++ testsuites/smptests/smpcapture02/smpc

[PATCH 1/2] doc: Describe new default error handler for Sparc

--- doc/cpu_supplement/sparc.t | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/doc/cpu_supplement/sparc.t b/doc/cpu_supplement/sparc.t index cd5602c..d21e9fe 100644 --- a/doc/cpu_supplement/sparc.t +++ b/doc/cpu_supplement/sparc.t @@ -951,10 +951,18 @@ handler

[PATCH] bsp/sparc: Move BSP_ISR_handler to a separate file

This allows it to be wrapped by another function at link-time and can be used to trace interrupts. If not placed in a separate file, the function pointer address used in BSP_shared_interrupt_init will be resolved at compile-time, and the function will not be wrappable. --- c/src/lib/libbsp/sparc/M

Trace interrupts with the capture engine

_vector_table[vector]); } -- Daniel Cederman Software Engineer Aeroflex Gaisler AB Aeroflex Microelectronic Solutions – HiRel Kungsgatan 12 SE-411 19 Gothenburg, Sweden ceder...@gaisler.com www.Aeroflex.com/Gaisler ___ devel mailing list devel@rtems.org ht

[PATCH v3 1/2] net: Add network task affinity config

This patch adds a default network tasks CPU affinity configuration option. The network drivers have the option to create their own daemon tasks with a custom CPU affinity set, or rely on the default set. --- cpukit/libnetworking/rtems/rtems_bsdnet.h | 9 ++ cpukit/libnetworking/rtems

[PATCH v3 2/2] nfs: Add RPCd task affinity config option

Similar to the task priority option, the new CPU affinity option is first controlled by the RPCI specific rpciodCpuset option. If that is not set, it uses the global network task config. If that is also not set, it falls back to not setting the affinity at all, using all CPUs. --- cpukit/libfs/src

Re: [PATCH v2 1/2] net: Add network task affinity config

An oversight. I've now added const to all cpuset references. On 2014-11-13 13:44, Sebastian Huber wrote: On 13/11/14 11:21, Daniel Cederman wrote: +cpu_set_t*network_task_cpuset; The consumer of this field (rtems_task_set_affinity()) uses a const cpuset, so why is this not

[PATCH v2 2/2] nfs: Add RPCd task affinity config option

From: Daniel Hellstrom Similar to the task priority option, the new CPU affinity option is first controlled by the RPCI specific rpciodCpuset option. If that is not set, it uses the global network task config. If that is also not set, it falls back to not setting the affinity at all, using all CP

[PATCH v2 1/2] net: Add network task affinity config

From: Daniel Hellstrom This patch adds a default network tasks CPU affinity configuration option. The network drivers have the option to create their own daemon tasks with a custom CPU affinity set, or rely on the default set. --- cpukit/libnetworking/rtems/rtems_bsdnet.h | 9 ++ c

Re: [PATCH 2/2] nfs: Add RPCd task affinity config option

On 2014-11-13 10:23, Sebastian Huber wrote: On 13/11/14 10:09, Daniel Cederman wrote: @@ -407,6 +410,8 @@ static rtems_intervalticksPerSec;/* cached system clock rate (WHO IS ASSUMED */ rtems_task_priorityrpciodPriority = 0

[PATCH 2/2] nfs: Add RPCd task affinity config option

From: Daniel Hellstrom Similar to the task priority option, the new CPU affinity option is first controlled by the RPCI specific rpciodCpuset option. If that is not set, it uses the global network task config. If that is also not set, it falls back to not setting the affinity at all, using all CP

[PATCH 1/2] net: Add network task affinity config

From: Daniel Hellstrom This patch adds a default network tasks CPU affinity configuration option. The network drivers have the option to create their own daemon tasks with a custom CPU affinity set, or rely on the default set. --- cpukit/libnetworking/rtems/rtems_bsdnet.h | 11

Re: Libatomic support

On 2014-10-02 15:09, Daniel Gutson wrote: On Thu, Oct 2, 2014 at 6:16 AM, Daniel Cederman wrote: I would not put too much time into this. Who needs this stuff? Thanks for the comment. I thought it would be a quick fix to add support, but looking at the code that gcc generates for _Atomic

Re: Libatomic support

y better to get an undefined reference error and make a custom solution than to add locks indirectly. So I will put this on hold. On 2014-10-02 07:50, Sebastian Huber wrote: On 01/10/14 16:20, Daniel Cederman wrote: I'm looking at GCC's libatomic, which provides software emulation of

Re: [PATCH] bsp/leon3: Replace the define LEON3_MP_IRQ with a weakly linked variable

, Sebastian Huber wrote: On 01/10/14 13:53, Daniel Cederman wrote: The LEON3_MP_IRQ define is used to pick the IRQ to be used by the shared memory driver and for inter-processor interrupts. On some LEON3 systems, for example the GR712RC, the default value of 14 is not suitable. To make this value

Libatomic support

Hi, I'm looking at GCC's libatomic, which provides software emulation of atomic operations that are not supported by hardware. It does this by using a compare-and-swap loop, or, failing that, using locks. At the moment it is not selected for compilation for RTEMS since it requires operating s

[PATCH] bsp/leon3: Replace the define LEON3_MP_IRQ with a weakly linked variable

The LEON3_MP_IRQ define is used to pick the IRQ to be used by the shared memory driver and for inter-processor interrupts. On some LEON3 systems, for example the GR712RC, the default value of 14 is not suitable. To make this value configurable from the application, it is replaced with a weakly link

Re: BSP specific settings

On 2014-09-30 16:45, Sebastian Huber wrote: If you need a link time option, then there is no standard way to do this on the BSP level. Most BSPs use some sort of weak tables or functions. The LEON3 BSP already uses such a thing for debug_uart_index for example. Ok, then I'll do something simil

BSP specific settings

Hi, I would like to add a way for the user of the leon3 bsp to specify the irq that should be used for IPIs. Is it adding an option to configure.ac for the bsp that is the recommended way? Or does there exist a supported way of setting bsp specific parameters similar to how it is done with co

[PATCH-V2] smptests/smpcache01: Remove invalidation of data cache lines from test

Invalidation of entire data cache might cause data written to the stack to get lost. --- testsuites/smptests/smpcache01/init.c | 47 +++ testsuites/smptests/smpcache01/smpcache01.doc | 1 - testsuites/smptests/smpcache01/smpcache01.scn | 18 -- 3 files chan

[PATCH] smptests/smpcache01: Remove invalidation of data cache lines from test

Invalidation of data cache lines might cause data written to the stack to get lost. --- testsuites/smptests/smpcache01/init.c | 45 +++ testsuites/smptests/smpcache01/smpcache01.doc | 2 -- testsuites/smptests/smpcache01/smpcache01.scn | 18 --- 3 files cha

[PATCH] smptests/smpcache01: Disable SMP cache manager test when not applicable

--- testsuites/smptests/smpcache01/init.c | 29 ++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/testsuites/smptests/smpcache01/init.c b/testsuites/smptests/smpcache01/init.c index dd2f9f1..48154d4 100644 --- a/testsuites/smptests/smpcache01/init.c +++

[PATCH V2] score: Define _CPU_Start_multitasking only for LEON SPARC, not SPARC in general

Rename _BSP_Start_multitasking to _LEON3_Start_multitasking to show that it is LEON specific --- c/src/lib/libbsp/sparc/leon3/startup/bspsmp.c |2 +- cpukit/score/cpu/sparc/rtems/score/cpu.h |6 -- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/c/src/lib/libbsp/spa

[PATCH] score: Define _CPU_Start_multitasking only for LEON SPARC, not SPARC in general

--- cpukit/score/cpu/sparc/rtems/score/cpu.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h index 9c38b55..d4c2ef0 100644 --- a/cpukit/score/cpu/sparc/rtems/score/cpu.h +++ b/cpukit/score/cpu/sparc/rtems

[PATCH] score: Add missing define to cache manager

--- c/src/lib/libcpu/shared/src/cache_manager.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index 7dd408f..7ff1166 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu

Re: arm/nds - cache_manager.c build failure

> Looks like this function needs a guard on #if > defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) Yes, looks like I missed that. I will send a patch. Daniel C On 2014-08-22 16:38, Gedare Bloom wrote: Looks like this function needs a guard on #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) see rtems_ca

Re: [Bug 2180] New: _TOD_Get_with_nanoseconds() is broken on SMP

Hi, We are currently experiencing this bug reported by Sebastian Huber and I could not find any discussion on it on the list. I'm guessing that the simple solution of moving the call to Clock_driver_support_at_tick() to the critical section of _TOD_Tickle_ticks() is not an acceptable solution

SMP Cache manager v3

Added commment on why I'm using BSP_fatal_exit instead of bsp_fatal and that it is required to flush the instruction cache also in single processor configuration. Rewrote cache manager so that it announces the operation and then releases the lock to avoid deadlocks. Added test program that invoke

[PATCH-v3 3/7] score: Add SMP support to the cache manager

Adds functions that allows the user to specify which cores that should perform the cache operation. SMP messages are sent to all the specified cores and the caller waits until all cores have acknowledged that they have flushed their cache. If CPU_CACHE_NO_INSTRUCTION_CACHE_SNOOPING is defined the i

[PATCH] smptests/smpcache01: Test the SMP cache manager

Invokes SMP cache management routines under different scenarios. --- testsuites/smptests/Makefile.am |1 + testsuites/smptests/configure.ac |1 + testsuites/smptests/smpcache01/Makefile.am| 19 ++ testsuites/smptests/smpcache01/init.c | 291 +++

[PATCH-v3 5/7] score/sparc: Add comment on icache flush after trap table update

Changes to the trap table might be missed by other cores. If the system state is up, the other cores can be notified using SMP messages that they need to flush their icache. If the up state has not been reached there is no need to notify other cores. They will do an automatic flush of the icache ju

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