The PSR register holds condition codes, the FPU enable bit, and similar,
which needs to be restored properly when switching task.
---
c/src/lib/libbsp/sparc/shared/irq_asm.S | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/c/src/lib/libbsp/sparc/shared/irq_asm.S
b/c/src/lib/libbsp/sparc/shared/irq_asm.S
index f7222e7..480bcbf 100644
--- a/c/src/lib/libbsp/sparc/shared/irq_asm.S
+++ b/c/src/lib/libbsp/sparc/shared/irq_asm.S
@@ -261,6 +261,14 @@ check_is_executing:
! Update the executing
st %g2, [%g6 + PER_CPU_OFFSET_EXECUTING]
+ ! Update PSR from new heir
+ ld [%o1 + PSR_OFFSET], %g1
+ and %o2, SPARC_PSR_CWP_MASK, %g3
+ andn %g1, SPARC_PSR_CWP_MASK, %g1
+ or %g1, %g3, %g1
+ or %g1, SPARC_PSR_ET_MASK, %g1
+ mov %g1, %psr
+
ba try_update_is_executing
mov 1, %g1
#endif
--
2.1.4
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