Re: [PATCH v1 3/4] aarch64/versal: Port JFFS2 GQSPI NOR Driver from Zynqmp

I agree with all of what you have said. I think it's best to leave this out for the moment and wait for the generic JFFS2 driver. If a need arises for it we can come back to it. --- Original Message --- On Friday, October 20th, 2023 at 12:43 AM, Kinsey Moore wrote: > It looks like thi

Re: [PATCH] fixed warning related to spstdc17

that didn't work but i'm thinking of defining a char array that is equal to the size of the processor lock and the isr lock? i figured that the processor lock is 64 bits and isr lock is a one bit? I'm confused on how to make an api define do you have a file i can look at? On Tue, 24 Oct 2023 a

[PATCH v3 1/2] bsps/clock: Import Xilinx TTC hardware definitions

This imports the TTC hardware definitions for the triple timer counters on various Xilinx platforms. This was imported as specified in the VERSION file in this commit. --- bsps/include/dev/clock/VERSION | 24 bsps/include/dev/clock/xttcps_hw.h | 207 + 2 files

[PATCH v3 2/2] bsps/arm: Add BSP for ZynqMP RPU

From: Philip Kirkpatrick --- .../console/console-config.c | 129 ++ bsps/arm/xilinx-zynqmp-rpu/include/bsp.h | 96 bsps/arm/xilinx-zynqmp-rpu/include/bsp/irq.h | 65 + bsps/arm/xilinx-zynqmp-rpu/include/tm27.h | 54 + bsps/arm/xilinx-zynqmp-

[PATCH v3 0/2] Add BSP for Cortex-R5 RPU

Changes from v2: * Fixed platform map installation * Fixed warnings in bspstartmpu.c * Fixed BSP internal function prototype name * Base Xilinx support contained in first two patches is now upstream ___ devel mailing list devel@rtems.org http://lists.rte

Re: [PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP

Great! I'll get those integrated and post a v3. Thanks, Kinsey On Tue, Oct 24, 2023 at 9:10 AM Philip Kirkpatrick < p.kirkpatr...@reflexaerospace.com> wrote: > Kinsey, > > I looked this over and built and tested it on actual hardware. I made the > minor changes below, but afterwards it worked a

Re: [PATCH v2 0/4] Add ZynqMP Cortex-R5 BSP

Kinsey, I looked this over and built and tested it on actual hardware. I made the minor changes below, but afterwards it worked as expected. The change to `bspmercuryxu5.yml` was required to allow my application to find `peripheral_maps/xilinx_zynqmp.h`. The other changes were not required, but

[PATCH] microblaze: Move interrupt context save to BSP

From: Sam Price The interrupt context save is now done in the BSP. This avoids an issue where a register is modified by the interrupt handler before it is saved. Specifically, the MSR register was modified by the `addi` instruction in the interrupt handler before the MSR was saved. This caused th

Re: [PATCH] fixed warning related to spstdc17

On 24.10.23 14:02, zack leung wrote: hi! sabestian did you mean the size of the structure? Yes, one option to get rid of the empty structures is to just provide typedefs, for example: #if defined(RTEMS_SMP) typedef struct Scheduler_Context { ... } Scheduler_Context; #else typedef struct S

Re: [PATCH] fixed warning related to spstdc17

hi! sabestian did you mean the size of the structure? On Mon, 23 Oct 2023 at 10:20, Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello Zack, > > there is a bit more work to do to fix this warning. The warning fix > should not result in a size increase of the uniprocessor RTEMS >