From: Sam Price <samuel.r.pr...@nasa.gov>
The interrupt context save is now done in the BSP. This avoids an issue
where a register is modified by the interrupt handler before it is
saved. Specifically, the MSR register was modified by the `addi`
instruction in the interrupt handler before the MSR was saved. This
caused the MSR to be saved with the wrong value.
Closes #4962
---
.../start/_interrupt_handler.S | 21 +++++++++++++++----
cpukit/score/cpu/microblaze/cpu_asm.S | 17 ---------------
2 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
index c24807c3e0..cf95eaee2f 100644
--- a/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
+++ b/bsps/microblaze/microblaze_fpga/start/_interrupt_handler.S
@@ -45,11 +45,24 @@
/* Subtract stack frame */
addik r1, r1, -(CPU_INTERRUPT_FRAME_SIZE)
- swi r5, r1, 8
+ /* Save stack frame */
+ swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
+ swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
+ swi r5, r1, MICROBLAZE_INTERRUPT_FRAME_R5
+ swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
+ swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
+ swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
+ swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
+ swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
+ swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
+ swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
+ swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
+ swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
+ swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
+ mfs r3, rmsr
+ swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
/* Indicate unknown interrupt source */
- addi r5, r0, 0xFF
-
braid _ISR_Handler
- nop
+ addik r5, r0, 0xFF
#endif /* __rtems__ */
diff --git a/cpukit/score/cpu/microblaze/cpu_asm.S
b/cpukit/score/cpu/microblaze/cpu_asm.S
index 0a2c5d8fff..b0bb2b1fa1 100644
--- a/cpukit/score/cpu/microblaze/cpu_asm.S
+++ b/cpukit/score/cpu/microblaze/cpu_asm.S
@@ -41,28 +41,11 @@
.align 2
_ISR_Handler:
- /* Save stack frame */
- swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_R3
- swi r4, r1, MICROBLAZE_INTERRUPT_FRAME_R4
- swi r6, r1, MICROBLAZE_INTERRUPT_FRAME_R6
- swi r7, r1, MICROBLAZE_INTERRUPT_FRAME_R7
- swi r8, r1, MICROBLAZE_INTERRUPT_FRAME_R8
- swi r9, r1, MICROBLAZE_INTERRUPT_FRAME_R9
- swi r10, r1, MICROBLAZE_INTERRUPT_FRAME_R10
- swi r11, r1, MICROBLAZE_INTERRUPT_FRAME_R11
- swi r12, r1, MICROBLAZE_INTERRUPT_FRAME_R12
- swi r15, r1, MICROBLAZE_INTERRUPT_FRAME_R15
- swi r18, r1, MICROBLAZE_INTERRUPT_FRAME_R18
- mfs r3, rmsr
- swi r3, r1, MICROBLAZE_INTERRUPT_FRAME_MSR
-
/* Disable dispatching */
lwi r3, r0, _Per_CPU_Information + 16
addik r3, r3, 1
swi r3, r0, _Per_CPU_Information + 16
- swi r14, r1, MICROBLAZE_INTERRUPT_FRAME_R14
-
/* Is SP < INTERRUPT_STACK_LOW? */
lwi r4, r0, _Per_CPU_Information
rsubk r3, r4, r1
--
2.34.1
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