Re: Strong APA Scheduler : First Draft

Hi Andrew, Your suggestion helps and I am going to work on it today. Thank you. On Thu, Jul 23, 2020 at 8:14 PM Andrew Butterfield < andrew.butterfi...@cs.tcd.ie> wrote: > Hi Richi, > > a quick answer to 1 below > > On 23 Jul 2020, at 15:20, Richi Dubey wrote: > 1)Both the algorithms require t

Re: [PATCH v2 2/2] break fenv.c file to function files

> On 24-Jul-2020, at 11:06 AM, Sebastian Huber > wrote: > > On 24/07/2020 07:35, Eshan Dhawan wrote: > -#include "../../fenv/fenv_stub.c" +#include + +int feclearexcept(int excepts) +{ +#ifndef __SOFTFP__ +fexcept_t __fpsr; + +vmrs_fpscr(_

Re: [PATCH v2 2/2] break fenv.c file to function files

On 24/07/2020 07:35, Eshan Dhawan wrote: -#include "../../fenv/fenv_stub.c" +#include + +int feclearexcept(int excepts) +{ +#ifndef __SOFTFP__ +fexcept_t __fpsr; + +vmrs_fpscr(__fpsr); +__fpsr &= ~excepts; +vmsr_fpscr(__fpsr); +#endif +return (0); +} Where is vmrs_fpscr() d

Re: [PATCH v2 2/2] break fenv.c file to function files

> On 24-Jul-2020, at 10:17 AM, Sebastian Huber > wrote: > > On 23/07/2020 21:41, Eshan dhawan wrote: > >> -#include "../../fenv/fenv_stub.c" >> +#include >> + >> +int feclearexcept(int excepts) >> +{ >> +#ifndef __SOFTFP__ >> +fexcept_t __fpsr; >> + >> +vmrs_fpscr(__fpsr); >> +__

[PATCH] eng: Add recommendations for attributes

Fix formatting. --- eng/coding-conventions.rst | 34 ++ 1 file changed, 30 insertions(+), 4 deletions(-) diff --git a/eng/coding-conventions.rst b/eng/coding-conventions.rst index 10034df..b85d8fc 100644 --- a/eng/coding-conventions.rst +++ b/eng/coding-conventions

Re: [PATCH rtems_waf 2/2] rtems: Add function to test waf uninstall

On 24/7/20 2:37 am, Vijay Kumar Banerjee wrote: > --- > rtems.py | 40 > 1 file changed, 40 insertions(+) > > diff --git a/rtems.py b/rtems.py > index 067a213..ab6d03b 100644 > --- a/rtems.py > +++ b/rtems.py > @@ -303,6 +303,46 @@ def build(bld): > i

Re: Is rtems available on a 4-cores cortex A72 (ARM-v8a) bsp?

On 24/07/2020 03:09, small...@aliyun.com wrote: 32-bit mode is OK. Does it fully support SMP and MMU in this bsp? RTEMS supports SMP on ARMv7-A and in particular the xilinx-zynqmp BSP. The MMU is statically set up. RTEMS doesn't support processes with virtual memory. _

Re: [PATCH v2 2/2] break fenv.c file to function files

On 23/07/2020 21:41, Eshan dhawan wrote: -#include "../../fenv/fenv_stub.c" +#include + +int feclearexcept(int excepts) +{ +#ifndef __SOFTFP__ + fexcept_t __fpsr; + + vmrs_fpscr(__fpsr); + __fpsr &= ~excepts; + vmsr_fpscr(__fpsr); +#endif + return (0); +} Where i

Re: [PATCH v2 1/2] Changed ARM fenv support similar to X86_64

Why didn't you use this patch https://sourceware.org/pipermail/newlib/2020/017780.html ? This patch is fine. It could be checked in as is. ___ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel

Re: Re: Is rtems available on a 4-cores cortex A72 (ARM-v8a) bsp?

32-bit mode is OK. Does it fully support SMP and MMU in this bsp? small...@aliyun.com From: Joel Sherrill Date: 2020-07-24 00:14 To: Sebastian Huber CC: small...@aliyun.com; devel Subject: Re: Is rtems available on a 4-cores cortex A72 (ARM-v8a) bsp? On Thu, Jul 23, 2020 at 7:25 AM Sebastian

Re: [GSoC 2020]: Weekly thread: Preparing RSB recipies for EPICS

Sorry for the inconvenience, Gedare, I will create another thread in relation with my doubts. I will also check about sed from here: https://docs.rtems.org/branches/master/user/testing/configuration.html and revert back to you! Thanks Mritunjay On Fri, Jul 24, 2020 at 4:35 AM Gedare Bloom wrot

Re: [GSoC 2020]: Weekly thread: Preparing RSB recipies for EPICS

On Thu, Jul 23, 2020 at 3:26 PM Mritunjay Sharma wrote: > > I have sent the Patches related to the RSB recipe of EPICS build > and I will request Chris and other mentors to kindly review and suggest > improvements. > > Also Chris, please can you help me how to ake it work across different BSPs /

Re: [PATCH 1/2] score: Add RTEMS_WEAK

On Thu, Jul 23, 2020 at 11:54 AM Sebastian Huber wrote: > > On 23/07/2020 19:19, Gedare Bloom wrote: > > > We don't have any specific rule, but all the examples in GCC docs put > > the attributes near the end of the line rather than in the > > start/middle. I mentioned this related to Christian's

Status of *AT functions in

I wrote a basic test file in Libbsd to see if the *at functions are present in libbsd But all the functions returned undefined reference Link to the test file : https://github.com/eshandhawan51/rtems-libbsd/blob/file_tests/testsuite/at_functions/test_main.c Link to the function table : https://docs

Re: [GSoC 2020]: Weekly thread: Preparing RSB recipies for EPICS

I have sent the Patches related to the RSB recipe of EPICS build and I will request Chris and other mentors to kindly review and suggest improvements. Also Chris, please can you help me how to ake it work across different BSPs / architectures? How to add some code to parameterize the EPICS configu

[PATCH rtems_rsb 4/4] Added sha512 hash for patch and source

Signed-off-by: Mritunjay Sharma --- rtems/config/epics/epics-7-1.cfg| 10 +++--- source-builder/config/epics-7-1.cfg | 2 -- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/rtems/config/epics/epics-7-1.cfg b/rtems/config/epics/epics-7-1.cfg index ed1f768..f9541d5 100644 --

[PATCH rtems_rsb 3/4] Added Patch for pc386 and EPICS build is working now

Signed-off-by: Mritunjay Sharma --- rtems/config/epics/epics-7-1.cfg| 28 rtems/config/epics/epics-base.bset | 26 ++ source-builder/config/epics-7-1.cfg | 6 ++ 3 files changed, 56 insertions(+), 4 deletions(-) create mode 100644 rt

[PATCH rtems_rsb 1/4] Initial step to build EPICS

Signed-off-by: Mritunjay Sharma --- source-builder/config/epics-7-1.cfg | 65 + 1 file changed, 65 insertions(+) create mode 100644 source-builder/config/epics-7-1.cfg diff --git a/source-builder/config/epics-7-1.cfg b/source-builder/config/epics-7-1.cfg new file mo

[PATCH rtems_rsb 2/4] Modified to fix 'can't cd' error

Signed-off-by: Mritunjay Sharma --- source-builder/config/epics-7-1.cfg | 20 1 file changed, 8 insertions(+), 12 deletions(-) diff --git a/source-builder/config/epics-7-1.cfg b/source-builder/config/epics-7-1.cfg index fe1fb45..ea25f28 100644 --- a/source-builder/config/ep

[PATCH v2 2/2] break fenv.c file to function files

Signed-off-by: Eshan dhawan --- newlib/libm/machine/arm/Makefile.am | 6 +- newlib/libm/machine/arm/Makefile.in | 34 +++- newlib/libm/machine/arm/fe_dfl_env.c | 38 +++- newlib/libm/machine/arm/feclearexcept.c | 45 - newlib/libm/machine/arm/fedisableexcept.c | 47 ++

[PATCH v2 1/2] Changed ARM fenv support similar to X86_64

Removed soft float files arm/fenv.c: Fix use of defines and format Fix the build. Remove superfluous code. Remove parameter names in the header file. Move implementation details out of the header file. Patch by: Eshan Dhawan and Sebastain huber Signed-off-by: Eshan dhawan --- newlib/lib

Re: [PATCH 1/2] score: Add RTEMS_WEAK

On 23/07/2020 19:19, Gedare Bloom wrote: We don't have any specific rule, but all the examples in GCC docs put the attributes near the end of the line rather than in the start/middle. I mentioned this related to Christian's recent patch with alignment attributes. It might be good for us to defin

Re: [PATCH 1/2] score: Add RTEMS_WEAK

We don't have any specific rule, but all the examples in GCC docs put the attributes near the end of the line rather than in the start/middle. I mentioned this related to Christian's recent patch with alignment attributes. It might be good for us to define some conventions for consistency. I lean t

Re: [PATCH 2/2] malloc: Make deferred free support optional

looks good, other than my comment on 1/2. On Thu, Jul 23, 2020 at 6:21 AM Sebastian Huber wrote: > > Only include the deferred free support if free() is actually used by the > application. > > The free() implementation in RTEMS supports that allocated memory is > freed in interrupt context. Sinc

[PATCH rtems-libbsd] wscript: add uninstall command

--- wscript | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/wscript b/wscript index 3ca9478e..74fc1f48 100644 --- a/wscript +++ b/wscript @@ -151,7 +151,7 @@ def bsp_init(ctx, env, contexts): # Transform the commands to per build variant commands commands = []

[PATCH rtems_waf 1/2] rtems: Add uninstall option to the list of commands

--- rtems.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtems.py b/rtems.py index ceabcd9..067a213 100644 --- a/rtems.py +++ b/rtems.py @@ -131,7 +131,7 @@ def init(ctx, filters = None, version = None, long_commands = False, bsp_init = # commands = []

[PATCH rtems_waf 2/2] rtems: Add function to test waf uninstall

--- rtems.py | 40 1 file changed, 40 insertions(+) diff --git a/rtems.py b/rtems.py index 067a213..ab6d03b 100644 --- a/rtems.py +++ b/rtems.py @@ -303,6 +303,46 @@ def build(bld): if bld.env.LONG_COMMANDS == 'yes': long_command_line() +de

Re: [PATCH rtems-tools] trace: Use c++14 instead of c++11 if possible

Hello Joel, On 22/07/2020 21:39, Joel Sherrill wrote: > > > On Wed, Jul 22, 2020 at 2:26 PM Christian Mauderer > wrote: > > Ping again. > > It's clearly not BSP specific. So I would like to get an approval for > that before pushing it anywhere. > > > C

Re: Is rtems available on a 4-cores cortex A72 (ARM-v8a) bsp?

On Thu, Jul 23, 2020 at 7:25 AM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > Hello, > > On 23/07/2020 07:52, small...@aliyun.com wrote: > > Hello， > > I have a TI bsp which uses a ARM cortex A72 process. It has 4 cores > > and MMU enabled. > > So does rtems support SMP and MMU in

Re: Strong APA Scheduler : First Draft

Hi Richi, a quick answer to 1 below > On 23 Jul 2020, at 15:20, Richi Dubey wrote: > 1)Both the algorithms require the use of a FIFO Queue to support the insert > and dequeue operations. > > I believe we can use chains and use the chain_append() and combination of > _Chain_Extract and _Chai

Re: Strong APA Scheduler : First Draft

Hi, The v1.1 of the draft is live at: https://richidubey.github.io/Strong-APA-Documentation/html/ and I need your reviews and your help on the following points: 1)Both the algorithms require the use of a FIFO Queue to support the insert and dequeue operations. I believe we can use chains and us

Re: Is rtems available on a 4-cores cortex A72 (ARM-v8a) bsp?

Hello, On 23/07/2020 07:52, small...@aliyun.com wrote: Hello， I have a TI bsp which uses a ARM cortex A72 process. It has 4 cores and MMU enabled. So does rtems support SMP and MMU in such a platform? After searching the mail and source code, I only find a cortex A53 platform. AArch64 is cu

[PATCH 0/2] malloc: Make deferred free support optional

Sebastian Huber (2): score: Add RTEMS_WEAK malloc: Make deferred free support optional cpukit/include/rtems/score/basedefs.h| 12 ++ cpukit/libcsupport/src/free.c| 43 ++ cpukit/libcsupport/src/malloc_deferred.c | 40 ++-- cpukit/libcsup

[PATCH 2/2] malloc: Make deferred free support optional

Only include the deferred free support if free() is actually used by the application. The free() implementation in RTEMS supports that allocated memory is freed in interrupt context. Since the heap is protected by a mutex, the frees issued in interrupt context cannot immediately be freed to the h

[PATCH 1/2] score: Add RTEMS_WEAK

Update #4032. --- cpukit/include/rtems/score/basedefs.h | 12 +++ testsuites/sptests/Makefile.am | 2 +- testsuites/sptests/spmisc01/init.c | 15 testsuites/sptests/spmisc01/spmisc01.h | 45 testsuites/sptests/spmisc01/strong.c | 47 +++

Re: Doubt regarding thread creation in RTEMS

Thank you for the clarification. On Thu, Jul 23, 2020 at 12:25 PM Sebastian Huber < sebastian.hu...@embedded-brains.de> wrote: > On 23/07/2020 08:12, Richi Dubey wrote: > > > I am still having a hard time understanding this. What do you mean by > > no code which blocks? Does the thread which exec