Re: [PATCH] libmisc/rtems-fdt: Add RTEMS FDT wrapper and shell command to libmisc.

On 16/08/2017 14:25, Chris Johns wrote: > - Provide application support for handling FDT blobs in RTEMS. This > is useful when interfacing FPGA fabrics. > - Provide a shell command to list a blob as well as provide read > and write access to addresses in the FTB. Posted v2 of the patch with th

[PATCH v2] libmisc/rtems-fdt: Add RTEMS FDT wrapper and shell command to libmisc.

- Provide application support for handling FDT blobs in RTEMS. This is useful when interfacing FPGA fabrics. - Provide a shell command to list a blob as well as provide read and write access to addresses in the FTB. Closes #3099. --- cpukit/Makefile.am |4 + cpukit

[PATCH] dev/i2c: Add I2C device support for FPGA Slave, LM25066A, TMP112, ADS1113 and ADS1115

Closes #3101. --- cpukit/dev/Makefile.am| 8 + cpukit/dev/i2c/fpga-i2c-slave.c | 132 + cpukit/dev/i2c/ti-ads-16bit-adc.c | 239 cpukit/dev/i2c/ti-lm25066a.c | 376 ++ cpukit/dev/i

[PATCH] dev/i2c: Add Xilinx AXI I2C driver.

This is a generic driver for use with Xilinx AXI I2C controller IP. Closes #3100. --- cpukit/dev/Makefile.am | 2 + cpukit/dev/i2c/xilinx-axi-i2c.c | 943 cpukit/dev/include/dev/i2c/xilinx-axi-i2c.h | 86 +++ cpukit/dev/preinstall.a

[PATCH] libmisc/rtems-fdt: Add RTEMS FDT wrapper and shell command to libmisc.

- Provide application support for handling FDT blobs in RTEMS. This is useful when interfacing FPGA fabrics. - Provide a shell command to list a blob as well as provide read and write access to addresses in the FTB. --- cpukit/Makefile.am |4 + cpukit/libmisc/Makefi

Re: RISC-V interrupts in HiFive1

On Wed, Aug 16, 2017 at 10:57 AM, Joel Sherrill wrote: > > > On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov > wrote: >> >> 2017-08-16 2:06 GMT+02:00 Hesham Almatary : >>> >>> / >>> >>> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov >>> wrote: >>> > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >>

Re: RISC-V interrupts in HiFive1

On Tue, Aug 15, 2017 at 7:50 PM, Denis Obrezkov wrote: > 2017-08-16 2:06 GMT+02:00 Hesham Almatary : > >> / >> >> On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov >> wrote: >> > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >> >> >> >> >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >> wrote:

Re: RISC-V interrupts in HiFive1

2017-08-16 2:06 GMT+02:00 Hesham Almatary : > / > > On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov > wrote: > > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> > >> > >> > >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" > wrote: > >> > >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > >>> > >>> Hi

Re: RISC-V interrupts in HiFive1

/ On Wed, Aug 16, 2017 at 3:03 AM, Denis Obrezkov wrote: > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: >> >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >>> >>> Hi Denis, >>> >>> You just need to modify riscv_interrupt_disable(). Read t

Re: RISC-V interrupts in HiFive1

2017-08-15 22:46 GMT+02:00 Denis Obrezkov : > 2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : >> >>> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >>> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: 2017-08-15 5:44 GMT+02:00

Does rtems-test work on MinGW64?

I have fixed the compile problems for the sis simulator on MinGW64, and I am now trying to run it through the rtems-test utility. This does however not work and gives the following error log: $ rtems-test --rtems-bsp=erc32-sis sparc-rtems4.12/c/erc32/testsuites RTEMS Testing - Tester, 4

Re: RISC-V interrupts in HiFive1

2017-08-15 20:38 GMT+02:00 Denis Obrezkov : > 2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > >> 2017-08-15 14:57 GMT+02:00 Joel Sherrill : >> >>> >>> >>> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >>> wrote: >>> >>> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >>> Hi Denis, You just n

Re: RISC-V interrupts in HiFive1

2017-08-15 19:03 GMT+02:00 Denis Obrezkov : > 2017-08-15 14:57 GMT+02:00 Joel Sherrill : > >> >> >> On Aug 15, 2017 4:32 AM, "Denis Obrezkov" >> wrote: >> >> 2017-08-15 5:44 GMT+02:00 Hesham Almatary : >> >>> Hi Denis, >>> >>> You just need to modify riscv_interrupt_disable(). Read the priv-spec

Re: RISC-V interrupts in HiFive1

2017-08-15 14:57 GMT+02:00 Joel Sherrill : > > > On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: > > 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > >> Hi Denis, >> >> You just need to modify riscv_interrupt_disable(). Read the priv-spec >> manual for your RISC-V version, and determine which bit s

Re: RISC-V interrupts in HiFive1

On Aug 15, 2017 4:32 AM, "Denis Obrezkov" wrote: 2017-08-15 5:44 GMT+02:00 Hesham Almatary : > Hi Denis, > > You just need to modify riscv_interrupt_disable(). Read the priv-spec > manual for your RISC-V version, and determine which bit should be > cleared (it's called MIE in priv-1.10, but you

Re: Patch preparation for GSoC evaluation

On Fri, Aug 11, 2017 at 12:21 PM, Denis Obrezkov wrote: > 2017-08-11 17:34 GMT+02:00 Christian Mauderer : >> >> Am 11.08.2017 um 17:24 schrieb Denis Obrezkov: >> > 2017-08-11 17:17 GMT+02:00 Christian Mauderer > > >: >> > >> > Am 11.08.2017 um 12:14 schrieb Denis Obr

Re: RISC-V interrupts in HiFive1

2017-08-15 5:44 GMT+02:00 Hesham Almatary : > Hi Denis, > > You just need to modify riscv_interrupt_disable(). Read the priv-spec > manual for your RISC-V version, and determine which bit should be > cleared (it's called MIE in priv-1.10, but you mentioned you work with > priv-1.9). > > Cheers, >