Re: [apache/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA #3009 (#3010)

The implementation of VTASimDPI does not seems to be loaded, perhaps a path issue in CMAKE files. -- Reply to this email directly or view it on GitHub: https://github.com/apache/tvm/pull/3010#issuecomment-1014641512 You are receiving this because you are subscribed to this thread. Message ID:

Re: [apache/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA #3009 (#3010)

I think the DPI interface changed (the verilog files [here](https://github.com/apache/tvm-vta/blob/36a91576edf633479c78649e050f18dd2ddc8103/hardware/chisel/src/main/resources/verilog/VTAMemDPI.v#L29-L42)), and the example (chisel) has to be update it to take into account that. -- Reply to this

[apache/tvm-vta] Fix simulation for new chisel release (#34)

The following fixes building simulation files for the new chisel version update done in #33 @tmoreau89 @ekiwi You can view, comment on, or merge this pull request online at: https://github.com/apache/tvm-vta/pull/34 -- Commit Summary -- * fix types -- File Changes -- M hardware/chi

Re: [apache/incubator-tvm] [VOTE] VTA HW/SW refactor (#5102)

`+1` -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/apache/incubator-tvm/issues/5102#issuecomment-601375010

[TVM Discuss] [Development] Getting started with the VTA Chisel backend

Hey, Well, it is been like two months, since I wrote this. All of this is already supported in mainstream TVM branch so no need for any of this. Those test are [here](https://github.com/dmlc/tvm/tree/master/vta/tests/python/integration) --- [Visit Topic](https://discuss.tvm.ai/t/getting-

[TVM Discuss] [Development] Getting started with the VTA Chisel backend

[quote="hjiang, post:13, topic:2987"] #1. When doing test_vta_insn.py I saw some test case get failed like “ALU MAX imm:False test took 1654 clock cycles”, could i know what is this ‘False’ means? [/quote] Check the print-message-code, the alu tests uses "immediate" as boolean. So, False means

[TVM Discuss] [Development] Getting started with the VTA Chisel backend

Yeah, I forgot to mention [this](https://docs.tvm.ai/vta/install.html#vta-simulator-installation) glad that you figured out. --- [Visit Topic](https://discuss.tvm.ai/t/getting-started-with-the-vta-chisel-backend/2987/11) to respond. You are receiving this because you enabled mailing lis

Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA #3009 (#3010)

Ok I have addressed most of the issues, except for `unsigned long long` complains cpplint is giving on arguments for DPI functions. The reason why I used this type is because this is the same type used by Verilator when it compiles 64-bit hardware types to C. -- You are receiving this because

Re: [dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA (#3009)

@jroesch There are two reasons why we have the two DPI modules in Verilog (Host and Memory): 1) To support either handwritten Verilog accelerators or generated Verilog from other languages different than Chisel3 2) Chisel3 does not support DPI, which is the "CFFI" of Verilog. However, Chisel

[dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA #3009 (#3010)

RFC in #3009 You can view, comment on, or merge this pull request online at: https://github.com/dmlc/tvm/pull/3010 -- Commit Summary -- * merge files * move verilator to the right place * change name to tsim -- File Changes -- M cmake/modules/VTA.cmake (5) A vta/apps/tsim/CMak

[dmlc/tvm] [RFC] [VTA] [TSIM] Enabling Cycle-Accurate Hardware Simulation for VTA (#3009)

The following RFC proposes a new simulation environment called *TSIM* that improves software and hardware integration and simulation accuracy compared to functional simulation. One of the goals of this RFC is integrating the hardware development process into the software stack from the beginning