@jroesch There are two reasons why we have the two DPI modules in Verilog (Host and Memory):
1) To support either handwritten Verilog accelerators or generated Verilog from other languages different than Chisel3 2) Chisel3 does not support DPI, which is the "CFFI" of Verilog. However, Chisel3 does support Verilog inlining which is what we use for this so we don't duplicate code, see [here](https://github.com/dmlc/tvm/pull/3010/files#diff-dd8e52a607ff89a3d150245f3a1af322R52) -- You are receiving this because you are subscribed to this thread. Reply to this email directly or view it on GitHub: https://github.com/dmlc/tvm/issues/3009#issuecomment-482747112
