I wrote the JSON and visualize the diagram at
https://neilturley.dev/netlistsvg/ , instead of generating from the Chisel
design directly.
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@isong @hht Thank you so much for your response. Although I've checked a bit
file is in /home/taeho/.vta_cache/pynq/0_0_1/1x16_i8w8a32_15_15_18_17.bit,
there was a problem. Instead, in the rpc_client.py, I've written bitstream =
"dir" which is the bit file directory I've saved in the local di
root@pynq:/home/xilinx# cat tvm/apps/vta_rpc/start_rpc_server_to_tracker.sh
#!/bin/bash
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
# re
Hi @thkim
I use `su` to start the tracker and modify the corresponding environment
variables.
```
TVM_HOME="/home/xilinx/tvm"
VTA_HW_PATH="/home/xilinx/tvm/3rdparty/vta-hw"
PYTHONPATH="/home/xilinx/tvm/python:/home/xilinx/tvm/topi/python:/home/xilinx/tvm/vta/python"
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Hi @thkim
Did you check if your bit file is at
`/home/taeho/.vta_cache/pynq/0_0_1/1x16_i8w8a32_15_15_18_17.bit"`?
In my case, I copy the bit file to the above dir.
I also use `sudo` to run tracker
```
pushd apps/vta_rpc
sudo -E ./start_rpc_server_to_tracker.sh
popd
```
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@isong @hht Thank you so much for your reply. I think I found a problem. When I
run the tutorial "Deploy Pretrained Vision Model from MxNet on VTA", I could
write a bitstream file to FPGA, and it worked well. I've written
vta.program_fpga(remote, bitstream="bitfiles/v4/1x16_i8w8a32_15_15_18_17
