On Fri, 30 May 2025 12:43:33 +0530
Gagandeep Singh wrote:
> This patch series introduces enhancements and fixes to the
> NXP DPAA2 Ethernet driver.
> It includes support for
> - software taildrop on ordered queues.
> - setup speed capabilities.
> - DPAA2 resource version.
> - MAC level stati
On Fri, 20 Jun 2025 13:27:07 +0200
Oleksandr Kolomeiets wrote:
> When sending a burst of output packets on a stopped transmit queue,
> the packets are written to a memory mapped address.
> On queue start the packets are processed and transmitted by the NIC.
>
> Signed-off-by: Oleksandr Kolomeiet
On Fri, 20 Jun 2025 13:27:04 +0200
Oleksandr Kolomeiets wrote:
> The following functions exported by the driver were stubs
> which merely changed the status flags:
> * rx_queue_start
> * rx_queue_stop
> * tx_queue_start
> * tx_queue_stop
>
> Proper implementation was added to con
On Sat, 28 Jun 2025 15:25:37 +0800
Feifei Wang wrote:
> +#define HINIC3_RX_EMPTY_THRESHOLD 3
> +u16
> +hinic3_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, u16 nb_pkts)
> +{
> + struct hinic3_rxq *rxq = rx_queue;
> + struct hinic3_rx_info *rx_info = NULL;
> + volatile struct hi
On Sat, 28 Jun 2025 15:25:24 +0800
Feifei Wang wrote:
> --- /dev/null
> +++ b/doc/guides/nics/hinic3.rst
> @@ -0,0 +1,51 @@
> +.. SPDX-License-Identifier: BSD-3-Clause
> +Copyright(c) 2025 Huawei Technologies Co., Ltd
> +
> +HINIC Poll Mode Driver
> +==
> +
> +The hinic3
On Wed, 18 Jun 2025 20:11:10 +0800
Wenbo Cao wrote:
> v1:
> *:fixed compile issue
> v0:
> *:fixed the below issue:
> Coverity issue: 468860,468866,468858
> Fixes: 4530e70f1e32 ("net/rnp: support Tx TSO offload")
> Fixes: 52dfb84e14be ("net/rnp: add device init and uninit")
>
On Wed, 11 Jun 2025 16:19:00 +0800
Dengdui Huang wrote:
> +#pragma pack(1)
> +#define HNS3_MBX_PRIO_SHIFT 4
> +#define HNS3_MBX_PRIO_MASK 0xFu
> +struct hns3_mbx_tc_config {
> + /*
> + * Each four bits correspond to one priority's TC.
> + * Bit0-3 correspond to priority-0's TC, b
27/06/2025 17:27, Bruce Richardson:
> In the case where we use the meson python "find_installation()" function
> to get our python binary, we can fail the configure/setup step if the
> elftools module is missing. This avoids later errors on build when the
> module is missed.
>
> Old output (error
18/06/2025 14:39, Marat Khalili:
> Test list is currently generated by scanning all files for macros
> starting with `REGISTER_` and ending with `_TEST`. Unfortunately, this
> was done line-by-line, and macros split into several lines were silently
> ignored resulting in tests being excluded from t
> Bing Zhao (5):
> net/mlx5: add new devarg for Tx queue consecutive memory
> net/mlx5: calculate the memory length for all Tx queues
> net/mlx5: allocate and release unique resources for Tx queues
> net/mlx5: pass the information in Tx queue start
> net/mlx5: use consecutive memory for T
12/06/2025 05:08, Stephen Hemminger:
> Prefer using simple structure assignment instead of memcpy.
> Using a structure assignment preserves type information and
> compiler checks types already.
>
> Signed-off-by: Stephen Hemminger
Applied, thanks.
24/06/2025 10:03, Morten Brørup:
> Coverity reports some defects, where the root cause seems to be negative
> return value from sysconf(_SC_PAGESIZE) not being handled.
> This series addresses those defects in the DPDK libraries.
>
> PS: "_SC_PAGESIZE" has the alias "_SC_PAGE_SIZE". Both are cover
16/06/2025 17:05, Jerin Jacob:
> On Mon, Jun 16, 2025 at 2:02 PM wrote:
> >
> > From: Pavan Nikhilesh
> >
> > Fix missing feature matrix addition for event device DMA and
> > vector adapters.
> >
> > Fixes: 66a30a29387a ("eventdev/dma: introduce DMA adapter")
> > Fixes: e12c3754da7a ("eventdev/ve
A new DPDK release candidate is ready for testing:
https://git.dpdk.org/dpdk/tag/?id=v25.07-rc2
There are 141 new patches in this snapshot.
Release notes:
https://doc.dpdk.org/guides/rel_notes/release_25_07.html
Most significant changes are in multiple drivers.
Please test and r
DLB2 port interrupt is implemented using DPDK interrupt
framework. This allows eventdev dequeue API to sleep when
the port queue is empty and gets wakeup when event arrives
at the port. Port dequeue mode is configured using devargs
argument port_dequeue_wait. Supported modes are polling and
interru
Update DPDK documentation for configuring DLB hardware history
list resource using devargs arguments.
Fixes: 33ab065d0c40 ("event/dlb2: support managing history list resource")
Signed-off-by: Pravin Pathak
---
doc/guides/eventdevs/dlb2.rst | 23 +++
1 file changed, 23 insert
Hi Stephen,
Thanks for your guidance, I will submit it next.
Regards Wenbo
> -Original Message-
> From: Stephen Hemminger
> Sent: 2025年6月30日 1:44
> To: Wenbo Cao
> Cc: dev@dpdk.org; yao...@mucse.com
> Subject: Re: [PATCH v0 0/3] [v0]drivers/net fixed Coverity issue
>
> On Wed, 18 Jun
Packets exceeding 64KB TSO size must be fragmented
across multiple descriptors,Otherwise,it may cause
TSO fragmentation anomalies.
Fixes: 4530e70f1e32 ("net/rnp: support Tx TSO offload")
Cc: sta...@dpdk.org
Signed-off-by: Wenbo Cao
Reviewed-by: Stephen Hemminger
---
drivers/net/rnp/rnp_rxtx.c
Adds support for boundary checking in the VLAN header
and corrects protocol header type verification.
Fixes: 4530e70f1e32 ("net/rnp: support Tx TSO offload")
Cc: sta...@dpdk.org
Signed-off-by: Wenbo Cao
Reviewed-by: Stephen Hemminger
---
drivers/net/rnp/rnp_rxtx.c | 70
This patchset primarily optimizes the robustness of code logic and
resolves anomalies in TSO segmentation.
v2:
* Optimized logical portability per Stephen Hemminger's suggestions
v1:
* fixed complie issue
v0:
*:fixed the below issue:
Coverity issue: 468860,468866,468858
Fixes
Add logic checks at critical points to detect potentially illegal
firmware information, preventing subsequent logic exceptions.
Fixes: 52aae4ed4ffb ("net/rnp: add device capabilities")
Fixes: 52dfb84e14be ("net/rnp: add device init and uninit")
Cc: sta...@dpdk.org
Signed-off-by: Wenbo Cao
Review
29/06/2025 00:49, Stephen Hemminger:
> On Sat, 28 Jun 2025 18:45:44 +0200
> Morten Brørup wrote:
>
> > > From: Thomas Monjalon [mailto:tho...@monjalon.net]
> > > Sent: Friday, 27 June 2025 20.30
> > >
> > > 27/06/2025 19:49, Morten Brørup:
> > > > > From: Thomas Monjalon [mailto:tho...@monjalo
26/06/2025 17:13, Thomas Monjalon:
> 26/06/2025 16:26, Stephen Hemminger:
> > On Wed, 25 Jun 2025 15:42:02 +0200
> > Thomas Monjalon wrote:
> >
> > > diff --git a/lib/ethdev/ethdev_linux_ethtool.c
> > > b/lib/ethdev/ethdev_linux_ethtool.c
> > > index ec42d3054a..f508cdba6c 100644
> > > --- a/lib
On Wed, 11 Jun 2025 12:40:33 +0530
vanshika.shu...@nxp.com wrote:
> -#define BMAN_BUF_MASK 0xul
> +RTE_EXPORT_INTERNAL_SYMBOL(bman_release_fast)
> +int
> +bman_release_fast(struct bman_pool *pool, const uint64_t *bufs,
> + uint8_t num)
> +{
> + struct bman_portal *p;
> +
On Wed, 11 Jun 2025 12:40:36 +0530
vanshika.shu...@nxp.com wrote:
> From: Vinod Pullabhatla
>
> Add support to set Tx rate on DPAA platform through PMD APIs
>
> Signed-off-by: Vinod Pullabhatla
> Signed-off-by: Vanshika Shukla
> ---
You intended to add a PMD specific API for rate limiting.
B
On Wed, 11 Jun 2025 12:40:31 +0530
vanshika.shu...@nxp.com wrote:
> + fd = open(FMAN_DEVICE_PATH, O_RDWR);
> + if (unlikely(fd < 0)) {
> + DPAA_BUS_LOG(ERR, "Unable to open (%s)", FMAN_DEVICE_PATH);
> + return fd;
> }
Would helpful to user if you added the er
On Wed, 11 Jun 2025 12:40:35 +0530
vanshika.shu...@nxp.com wrote:
> From: Jun Yang
>
> Adjust every element of pool by populate callback.
> 1) Make sure start DMA address is aligned with 16B.
> 2) For buffer across 4KB boundary, make sure start DMA address is
>aligned with 256B.
>
> Signed-
On Wed, 11 Jun 2025 12:40:37 +0530
vanshika.shu...@nxp.com wrote:
> diff --git a/doc/guides/nics/dpaa.rst b/doc/guides/nics/dpaa.rst
> index de3ae96e07..cc9aef7f83 100644
> --- a/doc/guides/nics/dpaa.rst
> +++ b/doc/guides/nics/dpaa.rst
> @@ -277,6 +277,9 @@ for details.
>
> * Use dev arg optio
On Wed, 28 May 2025 13:25:24 +0300
Shai Brandes wrote:
> This patchset includes an upgrade of the ENA HAL,
> introduces a new feature, and addresses three bug fixes.
>
> Thank you in advance to the net maintainers and community members
> for your time and effort reviewing the code.
>
> Best reg
Implement RTE_EVENT_DEV_CAP_CREDIT_PREALLOCATION.
Signed-off-by: Mattias Rönnblom
---
drivers/event/dsw/dsw_evdev.c | 5 ++-
drivers/event/dsw/dsw_evdev.h | 6 +++
drivers/event/dsw/dsw_event.c | 70 --
drivers/event/dsw/dsw_xstats.c | 3 ++
4 files changed,
Extend Eventdev API with an enqueue function for events of the
RTE_EVENT_OP_NEW_PREALLOCED operation type.
Signed-off-by: Mattias Rönnblom
---
lib/eventdev/eventdev_pmd.h | 2 +
lib/eventdev/eventdev_private.c | 1 +
lib/eventdev/rte_eventdev.h | 72
Implement rte_event_enqueue_new_prealloced_burst() in DSW.
Signed-off-by: Mattias Rönnblom
---
drivers/event/dsw/dsw_evdev.c | 1 +
drivers/event/dsw/dsw_evdev.h | 3 +++
drivers/event/dsw/dsw_event.c | 18 ++
3 files changed, 22 insertions(+)
diff --git a/drivers/event/dsw/ds
Optionally split the enqueue operation for new events into two steps;
allocating a "slot" for the event in the event device, and the actual
enqueue operation.
Pre-allocating credits reduces the risk of enqueue failures (i.e.,
backpressure) for new events. This is useful for applications
performing
Events of type RTE_EVENT_OP_NEW are often generated as a result of
some stimuli from the world outside the event machine. Examples of
such input can be a timeout in an application-managed timer wheel, a
control plane message on a lockless ring, an incoming packet
triggering the release of buffered
If the unique umem and MR method is enabled, before starting Tx
queues in device start stage, the memory will be pre-allocated
and the MR will be registered for the Tx queues' usage later.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 ++
drivers/net/mlx5/mlx5_trigger.c | 91
With this commit, a new device argument is introduced to control
the memory allocation for Tx queues.
By default, without specifying any value. A default alignment with
system page size will be used. All SQ / CQ memory of Tx queues will
be allocated once and a single umem & MR will be used.
When
The queue starting addresses offsets of a umem and doorbell offsets
are already passed to the Devx object creation function.
When the queue length is not zero, it means that the memory was
pre-allocated and the new object creation with consecutive memory
should be enabled.
When destroying the SQ
The actual Devx object of SQs and CQs are only created in the
function mlx5_txq_start() in the device stage.
By changing the 1-level iteration to 2-level iterations, the Tx
queue with a big number of queue depth will be set up firstly.
This will help to split the memory from big trunks to small tr
When the alignment is non-zero, it means that the single umem and MR
allocation for all Tx queues will be used.
In this commit, the total length of SQs and associated CQs will be
calculated and saved.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 +++
drivers/net/mlx5/mlx5_tx.h
This patchset will move all the mlx5 Tx queues memory to a
consecutive memory area. All the WQEBBs will be allocated based
on the offset of this memory area.
---
v2:
1. add a new fix for legacy code of WQE calculation
2. fix the style
v3:
1. change the devarg and add description.
2. reorga
If the unique umem and MR method is enabled, before starting Tx
queues in device start stage, the memory will be pre-allocated
and the MR will be registered for the Tx queues' usage later.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 ++
drivers/net/mlx5/mlx5_trigger.c | 91
The queue starting addresses offsets of a umem and doorbell offsets
are already passed to the Devx object creation function.
When the queue length is not zero, it means that the memory was
pre-allocated and the new object creation with consecutive memory
should be enabled.
When destroying the SQ
The actual Devx object of SQs and CQs are only created in the
function mlx5_txq_start() in the device stage.
By changing the 1-level iteration to 2-level iterations, the Tx
queue with a big number of queue depth will be set up firstly.
This will help to split the memory from big trunks to small tr
With this commit, a new device argument is introduced to control
the memory allocation for Tx queues.
By default, without specifying any value. A default alignment with
system page size will be used. All SQ / CQ memory of Tx queues will
be allocated once and a single umem & MR will be used.
When
When the alignment is non-zero, it means that the single umem and MR
allocation for all Tx queues will be used.
In this commit, the total length of SQs and associated CQs will be
calculated and saved.
Signed-off-by: Bing Zhao
---
drivers/net/mlx5/mlx5.h | 4 +++
drivers/net/mlx5/mlx5_tx.h
This patchset will move all the mlx5 Tx queues memory to a
consecutive memory area. All the WQEBBs will be allocated based
on the offset of this memory area.
---
v2:
1. add a new fix for legacy code of WQE calculation
2. fix the style
v3:
1. change the devarg and add description.
2. reorga
On Wed, 11 Jun 2025 11:09:53 +0800
Howard Wang wrote:
> This patch series includes the following updates:
>
> Add support for the RTL8168 1G NIC series.
> Add support for the RTL8127 10G NIC.
> Add support for the RTL8125CP NIC.
> Update hardware configuration for RTL8125 and RTL8126.
>
> Howar
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