On Wed, 11 Jun 2025 16:19:00 +0800
Dengdui Huang <huangdeng...@huawei.com> wrote:
> +#pragma pack(1)
> +#define HNS3_MBX_PRIO_SHIFT 4
> +#define HNS3_MBX_PRIO_MASK 0xFu
> +struct hns3_mbx_tc_config {
> + /*
> + * Each four bits correspond to one priority's TC.
> + * Bit0-3 correspond to priority-0's TC, bit4-7 correspond to
> + * priority-1's TC, and so on.
> + */
> + uint32_t prio_tc_map;
> + uint8_t tc_dwrr[HNS3_MAX_TC_NUM];
> + uint8_t num_tc;
> + /*
> + * Each bit correspond to one TC's scheduling mode, 0 means SP
> + * scheduling mode, 1 means DWRR scheduling mode.
> + * Bit0 corresponds to TC0, bit1 corresponds to TC1, and so on.
> + */
> + uint8_t tc_sch_mode;
> };
> +#pragma pack()
>
DPDK has portable macros for packing __rte_packed_begin and __rte_packed_end.
Please change to using those macros.
Then rebase, retest and resubmit this patcheset
