[PATCH] D152570: [clang] Apply -fmacro-prefix-map to anonymous tags in template arguments

zixuan-wu added a comment. Hi, Comment at: clang/test/CodeGenCXX/macro-prefix-map-lambda.cpp:11 + auto *s = lambdatest([](){}); +// CHECK: @"__PRETTY_FUNCTION__._Z10lambdatestIZ4mainE3$_0EDaOT_" = private unnamed_addr constant [{{[0-9]+}} x i8] c"auto lambdatest(f &&) [f = (l

[PATCH] D151397: [3/3][RISCV][POC] Model vxrm in C intrinsics for RVV fixed-point instruction vaadd, vasub

zixuan-wu added inline comments. Comment at: clang/include/clang/Basic/riscv_vector.td:1734 + __RISCV_VXRM_RDN = 2, + __RISCV_VXRM_ROD = 3, +}; I am wondering if we need a dynamic mode enum which representing using current vxrm value? Repository: rG LLVM

[PATCH] D153674: [dataflow] Disallow implicit copy of Environment, use fork() instead

zixuan-wu added a comment. Hi, there is a compiling error introduced recently as like following when files under clang/lib/Analysis/FlowSensitive/ are being compiled such as TypeErasedDataflowAnalysis.cpp and Transfer.cpp. Does anybody meet also? > from /usr/include/c++/7/functional:60, > f

[PATCH] D153674: [dataflow] Disallow implicit copy of Environment, use fork() instead

zixuan-wu added a comment. In D153674#4455357 , @sammccall wrote: > Hi, sorry about that - are you able to provide a full log, or link to a > failing bot? > That error message doesn't show where in the LLVM code the error occurs. It can pass with gcc 8.

[PATCH] D153674: [dataflow] Disallow implicit copy of Environment, use fork() instead

zixuan-wu added a comment. In D153674#4461195 , @sammccall wrote: > Sorry about the delay, and thanks for the `.i`. > > It took me a while to work out what was going on, but it looks like it's just > a bug where GCC forgets to automatic-move. > Fixed in

[PATCH] D148206: [clang] Do not crash after suggesting typo correction to constexpr if condition

zixuan-wu added inline comments. Comment at: clang/test/SemaCXX/invalid-if-constexpr.cpp:7 +} +void a() { if constexpr (__adl_swap<>) {}} // expected-error{{use of undeclared identifier '__adl_swap'; did you mean '__sync_swap'?}} \ + //

[PATCH] D142388: [clang] Add builtin_nondeterministic_value

zixuan-wu added inline comments. Comment at: clang/test/CodeGen/builtins-nondeterministic-value.c:26 +// CHECK-LABEL: entry +// CHECK: [[A:%.*]] = alloca double, align 8 +// CHECK: store double [[X:%.*]], ptr [[A]], align 8 hi, @ManuelJBrito , because double is 4

[PATCH] D141899: [IR][X86] Remove X86AMX type in LLVM IR instead of target extension

zixuan-wu added a comment. In D141899#4065375 , @nikic wrote: > In D141899#4061237 , @zixuan-wu > wrote: > >> With considering >> https://llvm.org/docs/DeveloperPolicy.html#ir-backwards-compatibility I >> think

[PATCH] D148124: [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

zixuan-wu added a comment. Thx. It has solved the issue D129824 . Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D148124/new/ https://reviews.llvm.org/D148124 ___ cfe-comm

[PATCH] D129824: [RISCV] Set triple based on -march flag which can be deduced in more generic way

zixuan-wu abandoned this revision. zixuan-wu added a comment. Herald added subscribers: jobnoorman, luke. As this issue is solved at https://reviews.llvm.org/D148124, abandon this revision. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D129824/new/ https://reviews.llvm.org/D129824

[PATCH] D142388: [clang] Add builtin_nondeterministic_value

zixuan-wu added inline comments. Comment at: clang/test/CodeGen/builtins-nondeterministic-value.c:26 +// CHECK-LABEL: entry +// CHECK: [[A:%.*]] = alloca double, align 8 +// CHECK: store double [[X:%.*]], ptr [[A]], align 8 ManuelJBrito wrote: > zixuan-wu wrote:

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

Zeson created this revision. Zeson added reviewers: nemanjai, sfertile, jtony, hfinkel, syzaara, lei, kbarton. Zeson added a subscriber: cfe-commits. It's mainly about signed and unsigned llvm builtins confusion. When function args are bool vector and signed vector, it should be mapped to signed

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

Zeson added a comment. In https://reviews.llvm.org/D27251#609014, @nemanjai wrote: > Thank you for fixing these issues. I certainly see how the shifts really need > to get the signedness right because the right shifts need to fill with the > sign bit (so that vector bool will still have all 0 o

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

Zeson updated this revision to Diff 79856. Zeson added a comment. Make vec_xst_be and vec_xl_be test cases put together seperately in `builtins-ppc-vsx.c` Move up macro `__VSX__` to make all vec_xst_be functions included https://reviews.llvm.org/D27251 Files: lib/Headers/altivec.h test/Cod

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

Zeson updated this revision to Diff 80021. Zeson marked 3 inline comments as done. Zeson added a comment. Remove some unnecessary cast https://reviews.llvm.org/D27251 Files: lib/Headers/altivec.h test/CodeGen/builtins-ppc-altivec.c test/CodeGen/builtins-ppc-p8vector.c test/CodeGen/built

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

Zeson added a comment. In https://reviews.llvm.org/D27251#610629, @kbarton wrote: > Please make explicit the signed for the parameters to the functions you are > changing and remove unnecessary casts. I marked the first few that I found, > but stopped marking them after the first several. I t

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

Zeson marked 2 inline comments as done. Zeson added a comment. Hi, All. The revision has been updated, please review it again. Thanks a lot. https://reviews.llvm.org/D27251 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.

[PATCH] D27251: [PPC] some bugs mainly about sign problem fixed in altivec.h

Zeson abandoned this revision. Zeson added a comment. I think this revision is out-of-date. I'd like to abandon it. https://reviews.llvm.org/D27251 ___ cfe-commits mailing list cfe-commits@lists.llvm.org http://lists.llvm.org/cgi-bin/mailman/listinf

[PATCH] D95589: [RISCV] Support experimental 'P' extension 0.9

zixuan-wu added a comment. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. Could abandon it due to D108189 ? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D95589/new/ https://reviews.llv

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. ping... CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3224284 , @jrtc27 wrote: > but also with RISC-V extensions not being changed once ratified any more > (changes mean new extensions entirely, not new versions) I don't think so. Or why is there version in RISC-V spec

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added inline comments. Comment at: llvm/lib/Support/RISCVISAInfo.cpp:48 {"v", RISCVExtensionVersion{0, 10}}, +//{"v", RISCVExtensionVersion{0, 7}}, {"zba", RISCVExtensionVersion{1, 0}}, jrtc27 wrote: > Don't do this This nit will be remove

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3224329 , @jrtc27 wrote: > In D115921#3224324 , @zixuan-wu > wrote: > >> In D115921#3224284 , @jrtc27 wrote: >> >>> but also with RI

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a comment. In D70401#3172750 , @khchen wrote: > In D70401#3172457 , @zixuan-wu wrote: > >> Hi, all. Why is it not continued? > > Sorry, I have to work on other tasks so stop the rv32e implementation

[PATCH] D70401: [WIP][RISCV] Implement ilp32e ABI

zixuan-wu added a subscriber: pcwang-thead. zixuan-wu added a comment. In D70401#3175266 , @khchen wrote: >> Is it (D70401 ) good enough to solve or >> complete rv32e issue? > > It need to > > 1. disallow ilp32e ABI with D

[PATCH] D108189: [RISCV] Support experimental 'P' extension 0.96

zixuan-wu added a comment. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence. Hi, @Jim. What time is P extension going to upstream to community since it's been no update for some months? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews

[PATCH] D115923: [RISCV][Don't Commit] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu created this revision. zixuan-wu added reviewers: asb, craig.topper, kito-cheng, luismarques, apazos, jrtc27, Jim, akuegel, jhenderson, MaskRay, sjarus. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, vkmr, frasercrmck, evandro, sameer.abuasal, s.egerton, be

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu created this revision. zixuan-wu added reviewers: asb, craig.topper, kito-cheng, luismarques, apazos, jrtc27, Jim, akuegel. Herald added subscribers: VincentWu, luke957, achieveartificialintelligence, armkevincheng, eric-k256, vkmr, frasercrmck, jdoerfert, evandro, sameer.abuasal, s.eg

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3201346 , @luismarques wrote: >> enable 'm' extension with passing mattr=+m After this patch, it would be >> -mattr=+m2p0. > > It's not obvious to me that support for extension versions should mean or has > to mean

[PATCH] D115923: [RISCV][Don't Commit] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu abandoned this revision. zixuan-wu added a comment. Only need review D115921 . Just abandon it. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115923/new/ https://reviews.llvm.org/D115923

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu updated this revision to Diff 395803. zixuan-wu edited the summary of this revision. zixuan-wu added a comment. Address comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added a comment. In D115921#3206156 , @jrtc27 wrote: > Do not bring back V draft 0.7. It is gone, it will never be supported again > by LLVM under that name. The standard extension namespace is reserved for > ratified extensions and developmen

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu added inline comments. Comment at: llvm/include/llvm/Support/RISCVISAInfo.h:33 + bool operator!=(const RISCVExtensionVersion &Version) const { +return !operator==(Version); + } craig.topper wrote: > Use `!(*this == Version)` Good taste.

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu updated this revision to Diff 396147. zixuan-wu edited the summary of this revision. zixuan-wu added a comment. Address all comments. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 Files: clang/lib/Basic/Targets/RISCV.cpp clang/

[PATCH] D115921: [RISCV] Refactor the RISCV ISA extension info and target features to support multiple extension version

zixuan-wu updated this revision to Diff 396148. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D115921/new/ https://reviews.llvm.org/D115921 Files: clang/lib/Basic/Targets/RISCV.cpp clang/lib/Driver/ToolChains/Arch/RISCV.cpp clang/test/Driver/riscv-arch-version.c llvm/include/llvm/

[PATCH] D105168: [RISCV] Unify the arch string parsing logic to RISCVISAInfo.

zixuan-wu added inline comments. Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp:107 + for (auto Feature : RISCVFeatureKV) { +if (FeatureBits[Feature.Value] && +llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key)) If Subtarg

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