zengdage wrote:
> Spacemit K1 is the name of the product/SoC or whatever you call it. The
> processor definitions in the RISCV backend are focusing on the CPU core. For
> Spacemit K1, the name of its core should be `X60`? I don't know……
@sunshaoce Hi, the `Spacemit-K1` is the SoC name and the
zengdage wrote:
Sorry, I misunderstand the 'readonly' meaning. So this pr is wrong.
https://github.com/llvm/llvm-project/pull/106499
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/zengdage closed
https://github.com/llvm/llvm-project/pull/106499
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
zengdage wrote:
@nikic @ChuanqiXu9 I am sorry to bother you again. Do you think the attribute
'nofree' should be added to 'this' pointer argument in c++ instance method ?
I think the 'this' pointer pointed to current object and it's life time is
guaranteed to be longer than the instance meth
https://github.com/zengdage reopened
https://github.com/llvm/llvm-project/pull/106499
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/zengdage edited
https://github.com/llvm/llvm-project/pull/106499
___
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
https://github.com/zengdage created
https://github.com/llvm/llvm-project/pull/119844
1. Rename LIBMVEC_X86 into LIBMVEC to support libmvec (glibc vector match
library) in risc-v.
2. Add RVVM1/2/4/8 in VFISAKind to distingusih the LMUL value, so we can take
full advantage of risc-v vector exte
https://github.com/zengdage updated
https://github.com/llvm/llvm-project/pull/119844
>From 101d7cb3749f0e3d892a7bf0bf797e40a334882f Mon Sep 17 00:00:00 2001
From: Zhijin Zeng
Date: Thu, 12 Dec 2024 11:42:32 +0800
Subject: [PATCH 1/2] [NFC] Add vector call tests if use vector-library in
risc-v
zengdage wrote:
@mga-sc Hi, can you help to review the pr? I add RVVM1/2/4/8 in VFISAKind to
support multiple LMUL value, maybe it can take full advantage of rvv register
group. Your pr (https://github.com/llvm/llvm-project/pull/114014) looks like
just support LMUL=2.
https://github.com/llvm/