I updated N32 patch for clang.
Simon Atanasyan via Phabricator
于2018年9月27日周四 下午8:23写道：
>
> atanasyan added a comment.
>
> Could you please update the patch against the current trunk?
>
>
> Repository:
> rC Clang
>
> https://reviews.llvm.org/D50850
>
>
>
--
YunQiang Su
wzssyqa wrote:
@brad0 can you have a look at this?
https://github.com/llvm/llvm-project/pull/71157
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wzssyqa wrote:
@brad0 can you have a look at this PR?
https://github.com/llvm/llvm-project/pull/68521
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https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/71157
On most hardware, FCSR.ABS2008 is set the value same with FCSR.NAN2008. Let's
use this behaivor by default.
With this commit, `clang -target mips -mnan=2008 -c fabs.c` will imply
`-mabs=2008`.
And of course, `
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/68521
>From 6053822322fd1594b46bf77c8b168ad802a7c534 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Sun, 8 Oct 2023 07:12:45 -0400
Subject: [PATCH] MIPS/libunwind: Use -mfp64 if compiler is FPXX
Libunwind supports F
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/71157
>From 4e1b075a26db2831d981bad61ae883ede890bd58 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Fri, 3 Nov 2023 03:30:52 -0400
Subject: [PATCH] Clang/MIPS: Use -mnan value for -mabs if not specified
On most hard
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/76894
On MIPS pre-R6, instruction b can only work within 64KiB,
which is not enough now.
We need the help of GOT.
For __mips64, we can get GOT by:
lui $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)
wzssyqa wrote:
@brad0
https://github.com/llvm/llvm-project/pull/76894
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https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/85174
MIPSr6 ISA requires normal load/store instructions support misunaligned memory
access, while it is not always do so by hardware. On some microarchitectures or
some corner cases it may need support by OS.
Don't
wzssyqa wrote:
> For MIPSr6, it is just like AARCH64, since some microarchitecture doesn't
> support mis-unaligned well in hardware level, so we need an options to
> disable it: kernel may need it.
>
> For GCC, we have `-mno-unalgined-access`. We need also add this option to
> clang.
https:/
@@ -321,9 +321,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
}
}
- if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
- options::OPT_munaligned_access)) {
-if (A->getOption().matches(options::OPT_mno_unalign
@@ -321,9 +321,11 @@ void aarch64::getAArch64TargetFeatures(const Driver &D,
}
}
- if (Arg *A = Args.getLastArg(options::OPT_mno_unaligned_access,
- options::OPT_munaligned_access)) {
-if (A->getOption().matches(options::OPT_mno_unalign
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/85174
>From e75523f5ab1bb58a495afdd30203a0c7c93c7ec4 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6
MIPSr6 ISA requires norma
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/85174
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https://github.com/llvm/llvm-project/pull/85174
>From 7e1cf74f4fc9271e88b62462ea9a38826fd3ee38 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Thu, 14 Mar 2024 11:48:36 +0800
Subject: [PATCH] MIPS: Support -m(no-)strict-align for r6
MIPSr6 ISA requires norma
https://github.com/wzssyqa closed
https://github.com/llvm/llvm-project/pull/85174
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https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/87256
TargetInfo has HasUnalignedAccess support now. For MIPSr6, we should set it
according strict-align.
For pre-R6, we always set strict-align and HasUnalignedAccess to false.
>From ecee40e72582c98e74e89d3aff97a832
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/87257
TargetInfo has HasUnalignedAccess support now. For MIPSr6, we should set it
according strict-align.
For pre-R6, we always set strict-align and HasUnalignedAccess to false.
>From ecee40e72582c98e74e89d3aff97a832
@@ -330,6 +331,8 @@ class LLVM_LIBRARY_VISIBILITY MipsTargetInfo : public
TargetInfo {
IsMicromips = true;
else if (Feature == "+mips32r6" || Feature == "+mips64r6")
HasUnalignedAccess = true;
+ else if (Feature == "+strict-align")
+StrictAli
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/87319
In ToolChain::getCompilerRT:
If none is found, use a file name from the new layout, which may get
printed in an error message, aiding users in knowing what Clang is
looking for.
But in current code, the old
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https://github.com/llvm/llvm-project/pull/87319
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https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From afacadad3f6654c60609a8d024ab9b6c0123195d Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/79116
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https://github.com/llvm/llvm-project/pull/79116
>From afacadad3f6654c60609a8d024ab9b6c0123195d Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 009bd230a51a1790e6691ae3f104f57af311272f Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/79116
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https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From af69ccc8182f8a1e86637b75a8fb1e717b157354 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/79116
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>From 65db5951e3c30b6c2a112b590839fad6b8ec2944 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Sun, 8 Oct 2023 07:12:45 -0400
Subject: [PATCH] MIPS/libunwind: Use -mfp64 if compiler is FPXX
Libunwind supports F
wzssyqa wrote:
Fangrui Song ***@***.***> 于2024年2月6日周二 13:36写道：
> Libunwind supports FP64 and FP32 modes, but not FPXX. The reason is that,
> FP64 and FP32 have different way to save/restore FPRs. If libunwind is
> built as FPXX, we have no idea which one should we use.
>
> Can you edit the descr
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/68521
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wzssyqa wrote:
@MaskRay
https://github.com/llvm/llvm-project/pull/79116
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https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/79116
Currently, clang accpets contraint f for softfloat, then LLVM meet an internal
error.
See: #64241
>From f01ce8f18a8cfaed41b4cfdd8b039abfc76aefd4 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 202
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/68521
Libunwind supports FP64 and FP32 modes, but not FPXX. The reason is that, FP64
and FP32 have different way to save/restore FPRs. If libunwind is built as
FPXX, we have no idea which one should we use.
If libunw
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 0ea3b2be9d364a042c7e7114b0f72fc3c144d2a0 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
@@ -0,0 +1,25 @@
+; RUN: llc -march=mips < %s | FileCheck %s --check-prefix=MIPS32
+; RUN: llc -march=mips64 < %s | FileCheck %s --check-prefix=MIPS64
+
+define dso_local void @read_double(double* nocapture noundef readonly %0)
local_unnamed_addr #0 {
wzssyqa w
@@ -0,0 +1,8 @@
+// RUN: %clang_cc1 -triple mips -target-feature +soft-float
-DSOFT_FLOAT_NO_CONSTRAINT_F -fsyntax-only -verify %s
+
+#ifdef SOFT_FLOAT_NO_CONSTRAINT_F
+void read_float(float* p) {
wzssyqa wrote:
Oh, yes. we can use `float p` here.
https://githu
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 838394878054831066e563fa243665ba6d68d824 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
wzssyqa wrote:
For MIPSr6, it is just like AARCH64, since some microarchitecture doesn't
support mis-unaligned well in hardware level, so we need an options to disable
it: kernel may need it.
For GCC, we have `-mno-unalgined-access`. We need also add this option to clang.
https://github.com/l
wzssyqa wrote:
> `-mno-unalgined-access` has been added since clang17:
> https://reviews.llvm.org/D149946
This option is for LoongArch instead of MIPSr6.
https://github.com/llvm/llvm-project/pull/65742
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https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/79116
>From 0da681135e785b01d67b0cef02581e0bba028ef3 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Jan 2024 18:14:48 +0800
Subject: [PATCH] MIPS/clang: Fix asm constraint for softfloat
This include 2 fixes:
@@ -132,6 +132,7 @@ class LLVM_LIBRARY_VISIBILITY LoongArch64TargetInfo
: LoongArchTargetInfo(Triple, Opts) {
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = Int64Type = SignedLong;
+HasCheapUnalignedBitfieldAccess = true;
--
@@ -132,6 +132,7 @@ class LLVM_LIBRARY_VISIBILITY LoongArch64TargetInfo
: LoongArchTargetInfo(Triple, Opts) {
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = Int64Type = SignedLong;
+HasCheapUnalignedBitfieldAccess = true;
--
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/65742
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@@ -132,6 +132,7 @@ class LLVM_LIBRARY_VISIBILITY LoongArch64TargetInfo
: LoongArchTargetInfo(Triple, Opts) {
LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
IntMaxType = Int64Type = SignedLong;
+HasCheapUnalignedBitfieldAccess = true;
--
@@ -368,14 +368,22 @@ macro(construct_compiler_rt_default_triple)
"Default triple for which compiler-rt runtimes will be built.")
endif()
- if ("${CMAKE_C_COMPILER_ID}" MATCHES "Clang")
+ if(CMAKE_C_COMPILER_ID MATCHES "Clang")
set(option_prefix "")
if
@@ -183,6 +183,24 @@ message(STATUS "LLVM default target triple:
${LLVM_DEFAULT_TARGET_TRIPLE}")
set(LLVM_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}")
+if(CMAKE_C_COMPILER_ID MATCHES "Clang")
+ set(option_prefix "")
+ if (CMAKE_C_SIMULATE_ID MATCHES "MSVC")
+set(opti
wzssyqa wrote:
> @wzssyqa Is it OK with you if I go ahead and merge this PR? I plan to follow
> up with further improvements but this is necessary to fix the build of LLVM
> runtime libraries in the bootstrapping build.
It is OK for me, while I have no permission to approve such a patch.
http
https://github.com/wzssyqa approved this pull request.
https://github.com/llvm/llvm-project/pull/87866
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wzssyqa wrote:
Replaced by: https://github.com/llvm/llvm-project/issues/87150
https://github.com/llvm/llvm-project/pull/87319
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wzssyqa wrote:
For me, I think that it is a good idea to always warn/hint the full/normalized
path.
For compatible reason, we can still try to find libraries in old-style or
non-full/normalized paths, while should not hint them.
https://github.com/llvm/llvm-project/pull/87866
_
https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/88334
Currently, clang looks for compiler-rt only from the normalized triple subdir.
While if we are configured with a non-normalized triple with
-DLLVM_DEFAULT_TARGET_TRIPLE, such as triples without vendor section, c
https://github.com/wzssyqa converted_to_draft
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wzssyqa wrote:
@aeubanks The problem is that in your configure, the libclang_rt is please in
`/lib/clang/19/lib/linux/libclang_rt.builtins-arm-android.a`, instead
of
`/lib/clang/19/lib/arm-unknown-linux-android/libclang_rt.builtins.a`.
https://github.com/llvm/llvm-project/pull/87866
__
wzssyqa wrote:
Configure cmd
```
cmake ../llvm -G Ninja -DLLVM_DEFAULT_TARGET_TRIPLE=aarch64-linux-gnu
-DLLVM_USE_LINKER=lld -DLLVM_ENABLE_RUNTIMES="compiler-rt;libunwind"
-DLLVM_ENABLE_PROJECTS="mlir;clang;clang-tools-extra;lld"
-DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++
-DCMAKE_B
wzssyqa wrote:
> > @aeubanks The problem is that in your configure, the libclang_rt is placed
> > in `/lib/clang/19/lib/linux/libclang_rt.builtins-arm-android.a`,
> > instead of
> > `/lib/clang/19/lib/arm-unknown-linux-android/libclang_rt.builtins.a`.
>
> The point is that both locations were
wzssyqa wrote:
> It's better to do some normalization in CMake.
I will try to work in CMake, then.
https://github.com/llvm/llvm-project/pull/88334
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wzssyqa wrote:
[xx.patch](https://github.com/llvm/llvm-project/files/14948921/xx.patch)
@aeubanks can you help to test this patch?
https://github.com/llvm/llvm-project/pull/87866
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https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/88661
Follow-up to #81037.
ToolChain::LibraryPaths holds the new compiler-rt library directory (e.g.
`/tmp/Debug/lib/clang/19/lib/x86_64-unknown-linux-gnu`). However, it might be
empty when the directory does not exi
wzssyqa wrote:
New PR with my resource-dir patch:
https://github.com/llvm/llvm-project/pull/88661
https://github.com/llvm/llvm-project/pull/87866
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@@ -16055,6 +16145,90 @@ of the two arguments. -0.0 is considered to be less
than +0.0 for this
intrinsic. Note that these are the semantics specified in the draft of
IEEE 754-2019.
+.. _i_minimumnum:
+
+'``llvm.minimumnum.*``' Intrinsic
+^
+
+
@@ -15883,6 +15883,95 @@ The returned value is completely identical to the
input except for the sign bit;
in particular, if the input is a NaN, then the quiet/signaling bit and payload
are perfectly preserved.
+.. _i_fminmax_family:
+
+'``llvm.min.*``' Intrinsics Comparation
@@ -15883,6 +15883,95 @@ The returned value is completely identical to the
input except for the sign bit;
in particular, if the input is a NaN, then the quiet/signaling bit and payload
are perfectly preserved.
+.. _i_fminmax_family:
+
+'``llvm.min.*``' Intrinsics Comparation
@@ -15883,6 +15883,95 @@ The returned value is completely identical to the
input except for the sign bit;
in particular, if the input is a NaN, then the quiet/signaling bit and payload
are perfectly preserved.
+.. _i_fminmax_family:
+
+'``llvm.min.*``' Intrinsics Comparation
@@ -15868,6 +15868,51 @@ The returned value is completely identical to the
input except for the sign bit;
in particular, if the input is a NaN, then the quiet/signaling bit and payload
are perfectly preserved.
+.. _i_fminmax_family:
+
+'``llvm.min.*``' Intrinsics Comparation
@@ -15868,6 +15868,51 @@ The returned value is completely identical to the
input except for the sign bit;
in particular, if the input is a NaN, then the quiet/signaling bit and payload
are perfectly preserved.
+.. _i_fminmax_family:
+
+'``llvm.min.*``' Intrinsics Comparation
https://github.com/wzssyqa closed
https://github.com/llvm/llvm-project/pull/93841
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https://github.com/wzssyqa created
https://github.com/llvm/llvm-project/pull/96281
We just introduce llvm.minimumnum and llvm.maximumnum intrinsics support to
llvm. Let's support them in Clang.
See: #93033
>From 5605426ee61ec58cad701103a43922b67792ccaf Mon Sep 17 00:00:00 2001
From: YunQiang
wzssyqa wrote:
@nikic thanks. Please also revert
https://github.com/llvm/llvm-project/commit/225d8fc8eb24fb797154c1ef6dcbe5ba033142da
https://github.com/llvm/llvm-project/pull/93841
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wzssyqa wrote:
@nikic Thanks. I submit an RFC now
https://discourse.llvm.org/t/rfc-fix-llvm-min-f-and-llvm-max-f-intrinsics/79735
https://github.com/llvm/llvm-project/pull/93841
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@@ -3636,6 +3648,22 @@ def Fmin : FPMathTemplate, LibBuiltin<"math.h"> {
let OnlyBuiltinPrefixedAliasIsConstexpr = 1;
}
+def FmaximumNum : FPMathTemplate, LibBuiltin<"math.h"> {
wzssyqa wrote:
Oh, newer libc does have this function:
https://www.gnu.org/sof
wzssyqa wrote:
Since we need to reuse some logic of `minnum/maxnum` to implement
`minimumnum/maximumnum`,
let's add them before switch the behavior of `minnum/maxnum`.
Known not working ports, will be fixed in future PRs:
1. X86: the current `minnum/maxnum` cannot process +0 vs -0 as
`minimu
wzssyqa wrote:
@peterwaller-arm I noticed that in
`llvm/test/CodeGen/AArch64/combine_andor_with_cmps.ll`, `FMAXNUM_IEEE` is
claimed that it is not supported. While I noticed that `fmaxnm` follows the
rules of `maxNUM` of IEEE754-2008.
Is there any other limitation of `fmaxnm`?
https://github.
wzssyqa wrote:
TODO: implement for architectures that don't have `fmin/fmax` instructions:
This is the example of MIPS pre-R6:
```
mins:
.setnoreorder
.setnomacro
mtc1$0,$f1
add.s $f0,$f12,$f1
add.s $f13,$f13,$f1
c.un.s $fcc0,$f0
@@ -16049,6 +16094,84 @@ of the two arguments. -0.0 is considered to be less
than +0.0 for this
intrinsic. Note that these are the semantics specified in the draft of
IEEE 754-2019.
+.. _i_minimumnum:
+
+'``llvm.minimumnum.*``' Intrinsic
+^
+
+
wzssyqa wrote:
> > 3. PowerPC: has some interaction with the behavior of `minnum/maxnum`: need
> > define `fcanonicalize`.
>
> AMDGPU has the same handling. This is to break the signaling nan handling
> from IEEE to the broken old glibc libm behavior. If we fix the definition to
> match IEEE,
@@ -631,6 +631,46 @@ TEST(APFloatTest, Maximum) {
EXPECT_TRUE(std::isnan(maximum(nan, f1).convertToDouble()));
}
+TEST(APFloatTest, MinimumNumber) {
+ APFloat f1(1.0);
+ APFloat f2(2.0);
+ APFloat zp(0.0);
+ APFloat zn(-0.0);
+ APFloat nan = APFloat::getNaN(APFloat::IEE
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/93841
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@@ -9130,6 +9142,15 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
if (visitBinaryFloatCall(I, ISD::FMAXNUM))
return;
break;
+ case LibFunc_fminimum_num:
+ case LibFunc_fminimum_numf:
+if (visitBinaryFloatCall(I, ISD::FMI
@@ -9130,6 +9142,15 @@ void SelectionDAGBuilder::visitCall(const CallInst &I) {
if (visitBinaryFloatCall(I, ISD::FMAXNUM))
return;
break;
+ case LibFunc_fminimum_num:
+ case LibFunc_fminimum_numf:
+if (visitBinaryFloatCall(I, ISD::FMI
@@ -32,27 +32,29 @@ class StoreInst;
/// These are the kinds of recurrences that we support.
enum class RecurKind {
- None, ///< Not a recurrence.
- Add, ///< Sum of integers.
- Mul, ///< Product of integers.
- Or, ///< Bitwise or logical OR of integers
wzssyqa wrote:
9f43a41db37253685c5ed428c215528eb92bbd43
1693009679313282afbed38778dd3fad62641e1b
Landed as the above commits.
https://github.com/llvm/llvm-project/pull/88661
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https://github.com/wzssyqa closed
https://github.com/llvm/llvm-project/pull/88661
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wzssyqa wrote:
See: https://github.com/llvm/llvm-project/pull/87866
Can you have a try to add an extra option
```
-resource-dir=%S/Inputs/resource_dir
```
https://github.com/llvm/llvm-project/pull/87866
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wzssyqa wrote:
Does it really needed?
https://github.com/llvm/llvm-project/pull/89425
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https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/89425
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https://github.com/wzssyqa requested changes to this pull request.
https://github.com/llvm/llvm-project/pull/89425
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@@ -142,7 +142,7 @@ if(WIN32 OR LLVM_WINSYSROOT)
set(RUNTIMES_${target}_CMAKE_MODULE_LINKER_FLAGS ${WINDOWS_LINK_FLAGS} CACHE
STRING "")
endif()
-foreach(target
aarch64-unknown-linux-gnu;armv7-unknown-linux-gnueabihf;i386-unknown-linux-gnu;riscv64-unknown-linux-gnu;x86_64-
@@ -181,6 +181,20 @@ message(STATUS "LLVM default target triple:
${LLVM_DEFAULT_TARGET_TRIPLE}")
set(LLVM_TARGET_TRIPLE "${LLVM_DEFAULT_TARGET_TRIPLE}")
+if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE)
+ set(print_target_triple ${CMAKE_CXX_COMPILER}
--target=${LLVM_RU
@@ -28,6 +28,19 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR)
if (NOT LLVM_RUNTIMES_BUILD)
load_llvm_config()
endif()
+ if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE)
wzssyqa wrote:
With my patch, `libclang_rt.builtin` has been inst
@@ -28,6 +28,19 @@ if (CMAKE_SOURCE_DIR STREQUAL CMAKE_CURRENT_SOURCE_DIR)
if (NOT LLVM_RUNTIMES_BUILD)
load_llvm_config()
endif()
+ if(LLVM_ENABLE_PER_TARGET_RUNTIME_DIR AND NOT APPLE)
+set(print_target_triple ${CMAKE_CXX_COMPILER}
--target=${LLVM_RUNTIME_TRIPLE}
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/89425
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@@ -656,19 +656,29 @@ std::string ToolChain::getCompilerRT(const ArgList &Args,
StringRef Component,
// Check for runtime files in the new layout without the architecture first.
std::string CRTBasename =
buildCompilerRTBasename(Args, Component, Type, /*AddArch=*/fals
https://github.com/wzssyqa updated
https://github.com/llvm/llvm-project/pull/89638
>From a40bf92dcdaa64c2ca73d9276972c8cd47750210 Mon Sep 17 00:00:00 2001
From: YunQiang Su
Date: Tue, 23 Apr 2024 01:36:17 +0800
Subject: [PATCH] Triple::normalize: Set OS for 3-component triple with none as
midd
https://github.com/wzssyqa edited
https://github.com/llvm/llvm-project/pull/89638
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