wangpc-pp wrote:
As @kito-cheng has pointed out, we should fix multilib issue before landing
this. It seems we don't generate multilib for ilp32f and lp64f in
riscv-gnu-toolchain?
https://github.com/llvm/llvm-project/pull/73489
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wangpc-pp wrote:
Please reorginize the patch as @dtcxzyw suggested. :-)
I didn't notice this extension before, so I may not be asking the right
question here: These MOPs can be redefined, then, are we able to schedule them
in compiler? Becase we don't know the cost of MOPs if we don't know how
wangpc-pp wrote:
> Please reorganize the patch as @dtcxzyw suggested. :-)
>
> I didn't notice this extension before, so I may not be asking the right
> question here: These MOPs can be redefined, then, are we able to schedule
> them in compiler? Becase we don't know the cost of MOPs if we don'
@@ -130,18 +138,18 @@ multiclass RVVVFNRCLIPBuiltinSet;
-defm sf_vqmacc_2x8x2 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)Sv(FixedSEW:8)v"]]>;
-defm sf_vqmaccus_2x8x2 : RVVVQMACCBuiltinSet<[["", "v",
"vv(FixedSEW:8)SUv(FixedSEW:8)v"]]>;
-defm sf_vqmaccsu_2x8x2 :
wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/74280
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https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/75182
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wangpc-pp wrote:
Add test in `clang/test/Driver/riscv-cpus.c`?
https://github.com/llvm/llvm-project/pull/75760
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@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
-check-pref
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
-check-pref
@@ -222,6 +222,11 @@
// MCPU-SIFIVE-X280-SAME: "-target-feature" "+zvl512b" "-target-feature"
"+zvl64b"
// MCPU-SIFIVE-X280-SAME: "-target-abi" "lp64d"
+// RUN: %clang -target riscv64 -### -c %s 2>&1
-menable-experimental-extensions -mcpu=sifive-p450 | FileCheck
-check-pref
@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280",
SiFive7Model,
[TuneSiFive7,
TuneDLenFactor2]>;
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+
https://github.com/wangpc-pp approved this pull request.
LGTM.
https://github.com/llvm/llvm-project/pull/75760
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https://github.com/wangpc-pp approved this pull request.
I have similar patch before: https://reviews.llvm.org/D125947, so it LGTM as
GCC's default behavior has changed. :-)
But please wait for others' opinions.
https://github.com/llvm/llvm-project/pull/73489
___
wangpc-pp wrote:
> short version: GCC isn't change. long version: GCC's configure script isn't
> change, it's configure script in riscv-gnu-toolchain
So why is there a difference between GCC and riscv-gnu-toolchain? If we set
`with_abi` to lp64f, what is the behavior?
>
> But I don't have str
https://github.com/wangpc-pp approved this pull request.
LGTM with nit.
https://github.com/llvm/llvm-project/pull/73971
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@@ -171,18 +171,12 @@ void riscv::getRISCVTargetFeatures(const Driver &D, const
llvm::Triple &Triple,
Features.push_back("-save-restore");
// -mno-unaligned-access is default, unless -munaligned-access is specified.
- bool HasV = llvm::is_contained(Features, "+zve32x")
@@ -180,13 +180,10 @@ void emitCodeGenSwitchBody(const RVVIntrinsic *RVVI,
raw_ostream &OS) {
return;
}
- // Cast pointer operand of vector load intrinsic.
for (const auto &I : enumerate(RVVI->getInputTypes())) {
wangpc-pp wrote:
Why not remove thi
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/74280
We can reduce some code.
>From 1a9364a8b1e0eae320774253ac98a445daf7ec9f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 4 Dec 2023 14:11:19 +0800
Subject: [PATCH] [RISCV][NFC] Use AddTargetFeature to add
fa
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76357
This PR implements the draft
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36.
Currently, we replace specified profile in `-march` with standard
arch string.
We may need to pass it to backe
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 806babf92282735c364b7ac88faa5256d04f2742 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR impleme
wangpc-pp wrote:
Should this be rebased on
Zimop(https://github.com/llvm/llvm-project/pull/75182) commit? Though I don't
know why it has been merged yet...
https://github.com/llvm/llvm-project/pull/66043
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wangpc-pp wrote:
It seems that the author of Zimop implementation doesn't have commit access.
@yetingk Would you mind to commit it and rebase your PR on that? It will make
this PR simpler.
https://github.com/llvm/llvm-project/pull/66043
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76387
The arch string may not start with rv32/rv64 if we have supported
profiles in `-march`.
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +08
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76387
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +0800
Subject: [PATCH 1/2] [RISCV][NFC] Use RISCVISAInfo instead of string
comparison
The a
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76395
This implements experimental support for the Zcmop extension as
specified here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc.
This change adds only MC support.
>From 20fd01b09bb196cf538
@@ -0,0 +1,71 @@
+//===-- RISCVInstrInfoZicfiss.td - RISC-V Zicfiss -*- tablegen
-*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apa
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76395
>From 20fd01b09bb196cf53807b44161482d56a43920b Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 20:46:13 +0800
Subject: [PATCH 1/3] [RISCV][MC] Add support for experimental Zcmop extension
This imp
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76387
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +0800
Subject: [PATCH 1/3] [RISCV][NFC] Use RISCVISAInfo instead of string
comparison
The a
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76429
To reduce calls to `consumeError`.
>From 0d8426ffb1202ceca97b25c0dd47d516c1be280e Mon Sep 17 00:00:00 2001
From: wangpc
Date: Wed, 27 Dec 2023 14:41:30 +0800
Subject: [PATCH] [RISCV][NFC] Use errorToBool
To
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76387
>From ed8ebdb6f2133f84d1f5a8d2cd580dba4ceed922 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Tue, 26 Dec 2023 15:58:10 +0800
Subject: [PATCH 1/4] [RISCV][NFC] Use RISCVISAInfo instead of string
comparison
The a
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 965c1c682d16a3f47c563a301c89e3717bf4d1c5 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR impleme
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From f4ca1ac0dedf5af0d9ddf05f7a67f30091b296ee Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR impleme
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/76429
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>From fa079e4be8b1b043b635a494b8c0bcc5aa79092b Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RFC][RISCV] Support RISC-V Profiles in -march option
This PR impleme
W-angler wrote:
Current implementation is based on the
comment(https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/36#issuecomment-1867859642),
not the RFC. @dtcxzyw
https://github.com/llvm/llvm-project/pull/76357
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https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/76893
It seems that we have `B` extension again: https://github.com/riscv/riscv-b
According to the spec, `B` extension represents the collection of
the `Zba`, `Zbb`, `Zbs` extensions.
Though it hasn't been ratified,
wangpc-pp wrote:
> > I would suggest set it as 0.1 rather than 1.0, and I gonna to ask Ved to
> > add version info as well...
>
> Then also needs to move behind -menable-experimental-extensions.
Yes, this is why I set version to 1.0.
All implied extensions are ratified but when we want to use
wangpc-pp wrote:
> @wangpc-pp did you have interested on helping psABI side? it would be great
> if you can help since I suspect I don't have enough bandwidth to deal with
> that soon.
Yes, I'm glad to. I think what we need to do is to fix some Zdinx issues? :-)
And, I think I have to explain
@@ -42,9 +42,10 @@ static bool getArchFeatures(const Driver &D, StringRef Arch,
return false;
}
- (*ISAInfo)->toFeatures(
- Features, [&Args](const Twine &Str) { return Args.MakeArgString(Str); },
- /*AddAllExtensions=*/true);
+ const auto ISAInfoFeatures = (
wangpc-pp wrote:
> Side note: shouldn't we also update `compiler-rt/lib/builtins/riscv/{save,
> restore}.S`? E.g. with something like this:
> [...]
> (I don't remember why exactly since I did it a long time ago, but for some
> reason I do have this patch in my LLVM fork, so it probably was nec
wangpc-pp wrote:
> > As for your diffs, it seems that you only handle the
> > `__riscv_save/restore_[2|1|0]`, which is incomplete. And the code is not
> > different with non-rve cases?
>
> Yes, I mostly copy-pasted the existing code and removed all of the code
> dealing with registers not ava
https://github.com/wangpc-pp created
https://github.com/llvm/llvm-project/pull/77424
`A` extension has been split into two parts: Zaamo (Atomic Memory
Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also
https://github.com/riscv/riscv-zaamo-zalrsc.
This patch adds the basic compil
@@ -0,0 +1,11 @@
+# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zaamo < %s 2>&1 |
FileCheck %s
wangpc-pp wrote:
This can be done in the future, I think.
Current implementation refers to the `Zmmul` (which is a sub-extension of M
extension). The case i
@@ -17,6 +17,13 @@ def HasStdExtZicsr :
Predicate<"Subtarget->hasStdExtZicsr()">,
AssemblerPredicate<(all_of FeatureStdExtZicsr),
"'Zicsr' (CSRs)">;
+def FeatureStdExtI
+: SubtargetFeature<"i", "HasStdExtI",
@@ -83,13 +88,14 @@ RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction
*MF) const {
}
BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
+ const RISCVSubtarget &STI = MF.getSubtarget();
wangpc-pp wrote:
This should be a
@@ -985,9 +1003,10 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
};
for (auto Reg : CSRegs)
- SavedRegs.set(Reg);
+ if (Reg < RISCV::X16 || !Subtarget.isRVE())
wangpc-pp wrote:
The psABI says:
> If used with an ISA t
@@ -386,6 +393,11 @@ bool
RISCVTargetInfo::handleTargetFeatures(std::vector &Features,
if (llvm::is_contained(Features, "+experimental"))
HasExperimental = true;
+ if (ABI == "ilp32e" && ISAInfo->hasExtension("d")) {
+Diags.Report(diag::err_invalid_feature_combinat
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/76777
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The doc is not correctly rendered with missing blank lines.
>From 2d249aefa1bfa91f41a3866c4203eff041415546 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Wed, 10 Jan 2024 17:54:27 +0800
Subject: [PATCH] [Clang][
https://github.com/wangpc-pp closed
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@@ -985,9 +1003,10 @@ void
RISCVFrameLowering::determineCalleeSaves(MachineFunction &MF,
};
for (auto Reg : CSRegs)
- SavedRegs.set(Reg);
+ if (Reg < RISCV::X16 || !Subtarget.isRVE())
wangpc-pp wrote:
Though it's nearly impossible to have s
wangpc-pp wrote:
I think we will add attributes automatically?
```shell
~/workspace# cat a.S
.globl foo
.p2align1
.type foo,@function
foo:
ret
~/workspace# clang -march=rv64gcv -c a.S
~/workspace# llvm-readobj -A a.o
File: a.o
Format: elf64-littleriscv
Arch:
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option
This PR implemen
@@ -854,6 +895,30 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 8dc42f5c90ba369a145868f8c1a9a8cb3e988cb0 Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option
This PR implemen
wangpc-pp wrote:
I support adding these builtins personally, but I think we need more
discussions on the design.
We can achieve the same thing via inline assemblies, that's true. But, from the
compiler side, inline assemblies are kind of barriers, we can't do a lot of
optimizations/reorderings
wangpc-pp wrote:
> > > I support adding these builtins personally, but I think we need more
> > > discussions on the design. We can achieve the same thing via inline
> > > assemblies, that's true. But, from the compiler side, inline assemblies
> > > are kind of barriers, we can't do a lot of o
wangpc-pp wrote:
> We discussed this on the sync-up call and @preames very rightly pointed out
> that we should take a step back here...from a user perspective, what does
> specifying a profile via `-mcpu` provide that specifying it via `-march`
> doesn't? We weren't able to answer that in the
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
wangpc-pp wrote:
GCC gained its `__arm_rsr` and `__arm_wsr` support last year (October, 2023):
https://gcc.gnu.org/pipermail/gcc-patches/2023-October/631855.html. So there is
no stable released GCC version that supports these builtins.
Clang supported these builtins about nine years ago:
https
https://github.com/wangpc-pp approved this pull request.
LGTM. cc @asb @topperc
Some context of RISCV target:
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/62
https://github.com/llvm/llvm-project/pull/85350
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wangpc-pp wrote:
> Should we use strings like ARM does so we can get register by name?
Good point! We may provide two kinds of builtins: one by name, and another by
CSR number.
We should continue @lenary's proposal and discuss it in
https://github.com/riscv-non-isa/riscv-toolchain-conventions
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH] [RISCV] Support RISC-V Profiles in -march option
This PR implements t
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
@@ -854,6 +854,81 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool
EnableExperimentalExtension,
"string must be lowercase");
}
+ bool IsProfile = Arch.starts_with("rvi") || Arch.starts_with("rva") ||
+ Arch.starts_with("r
wangpc-pp wrote:
There is a Windows failure that I can't reproduce:
https://buildkite.com/llvm-project/github-pull-requests/builds/46331
Can someone help me to figure out what is wrong?
https://github.com/llvm/llvm-project/pull/83774
___
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/2] [RISCV] Support RISC-V Profiles in -march option
This PR implemen
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/76357
>From 28000eb88b54b02993107d4f222acc5d733c623f Mon Sep 17 00:00:00 2001
From: wangpc
Date: Mon, 25 Dec 2023 18:52:36 +0800
Subject: [PATCH 1/3] [RISCV] Support RISC-V Profiles in -march option
This PR implemen
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From 26245679b0f40b510e628aaed091739e9931c29c Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/5] [clang] Enable sized deallocation by default in C++14
onwards
Si
wangpc-pp wrote:
This breaks CI `Test documentation build` like:
https://github.com/llvm/llvm-project/actions/runs/8339765845/job/22822367034
https://github.com/llvm/llvm-project/pull/83149
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https
wangpc-pp wrote:
> > > There is a Windows failure that I can't reproduce:
> > > https://buildkite.com/llvm-project/github-pull-requests/builds/46331 Can
> > > someone help me to figure out what is wrong?
> >
> >
> > I'm not certain what's going on yet, but it smells a bit like the
> > interp
wangpc-pp wrote:
> > Not entirely certain what you're asking, but MSVC CRT does have a
> > definition for sized delete:
> > ```
> > _CRT_SECURITYCRITICAL_ATTRIBUTE
> > void __CRTDECL operator delete(void* const block, size_t const) noexcept
> > {
> > operator delete(block);
> > }
> > ```
> >
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Author: Wang Pengcheng
Date: 2024-03-22T18:49:25+08:00
New Revision: 6e755c51a916dc521ffe89738bcab47a5442ad06
URL:
https://github.com/llvm/llvm-project/commit/6e755c51a916dc521ffe89738bcab47a5442ad06
DIFF:
https://github.com/llvm/llvm-project/commit/6e755c51a916dc521ffe89738bcab47a5442ad06.diff
Author: Wang Pengcheng
Date: 2024-03-22T23:21:11+08:00
New Revision: b44771f480385fa93ba7719a57e759e19747e709
URL:
https://github.com/llvm/llvm-project/commit/b44771f480385fa93ba7719a57e759e19747e709
DIFF:
https://github.com/llvm/llvm-project/commit/b44771f480385fa93ba7719a57e759e19747e709.diff
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/2] [clang] Enable sized deallocation by default in C++14
onwards
Si
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/3] [clang] Enable sized deallocation by default in C++14
onwards
Si
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/4] [clang] Enable sized deallocation by default in C++14
onwards
Si
https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/83774
>From f1653805def59bc6eb23052b3ade80c900b4daaa Mon Sep 17 00:00:00 2001
From: wangpc
Date: Fri, 14 Jul 2023 10:38:14 +0800
Subject: [PATCH 1/5] [clang] Enable sized deallocation by default in C++14
onwards
Si
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/84877
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https://github.com/wangpc-pp updated
https://github.com/llvm/llvm-project/pull/84877
>From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001
From: Wang Pengcheng
Date: Tue, 12 Mar 2024 14:28:09 +0800
Subject: [PATCH 1/2] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=
=
https://github.com/wangpc-pp edited
https://github.com/llvm/llvm-project/pull/84448
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https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/84448
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@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
wangpc-pp wrote:
Windows CI is passed now, many thanks to @AaronBallman @vgvassilev!
I may land this in a few days if there is no more comment. :-)
https://github.com/llvm/llvm-project/pull/83774
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@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
@@ -49,3 +49,62 @@ if ((MINGW OR CYGWIN) AND BUILD_SHARED_LIBS)
# despite potential dllexports.
target_link_options(clangInterpreter PRIVATE LINKER:--export-all-symbols)
endif()
+
+if(MSVC)
+ set_target_properties(clangInterpreter PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS
1)
wangpc-pp wrote:
Ping for comments.
https://github.com/llvm/llvm-project/pull/79975
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wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/80279
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wangpc-pp wrote:
> The changes seem reasonable to me but I'd feel more comfortable if the
> functionality was also being used (so that we'd get test coverage verifying
> its correctness). Do you think it would be reasonable to include the RISCV
> changes as well?
Yeah, I separated RISCV chang
https://github.com/wangpc-pp closed
https://github.com/llvm/llvm-project/pull/80279
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https://github.com/wangpc-pp commented:
The code is OK I think.
One question: how will these builtins be used? Are their semantics bound to
specific extensions that extend MOPs?
https://github.com/llvm/llvm-project/pull/79971
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wangpc-pp wrote:
Ping.
https://github.com/llvm/llvm-project/pull/76357
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