================
@@ -216,6 +216,25 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280",
SiFive7Model,
[TuneSiFive7,
TuneDLenFactor2]>;
+def SIFIVE_P450 : RISCVProcessorModel<"sifive-p450", NoSchedModel,
+ [Feature64Bit,
+ FeatureStdExtZifencei,
+ FeatureStdExtM,
+ FeatureStdExtA,
+ FeatureStdExtF,
+ FeatureStdExtD,
+ FeatureStdExtC,
+ FeatureStdExtZicbop,
+ FeatureStdExtZicbom,
+ FeatureStdExtZicboz,
+ FeatureStdExtZihintntl,
+ FeatureStdExtZihintpause,
+ FeatureStdExtZihpm,
+ FeatureStdExtZba,
+ FeatureStdExtZbb,
+ FeatureStdExtZbs,
+ FeatureStdExtZfhmin]>;
+
----------------
wangpc-pp wrote:
I don't find the supported ISA description in datasheet, so I wonder if it's
true that only `Zfhmin` is implemented. Should it be `Zfh`?
https://github.com/llvm/llvm-project/pull/75760
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